Simulation Results: hmac

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.81 %
  • code
  • 99.28 %
  • assert
  • 97.14 %
  • func
  • 100.00 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.96 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.990s 2808.386us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.340s 68.592us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.290s 105.350us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 10.910s 2947.293us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 8.980s 3426.619us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 900.910s 101033.281us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.290s 105.350us 20 20 100.00
hmac_csr_aliasing 8.980s 3426.619us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 79.890s 8963.499us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 78.680s 1437.739us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 261.390s 18411.647us 30 30 100.00
hmac_test_sha384_vectors 596.290s 13998.807us 75 75 100.00
hmac_test_sha512_vectors 537.720s 15762.297us 75 75 100.00
hmac_test_hmac256_vectors 16.040s 356.388us 50 50 100.00
hmac_test_hmac384_vectors 18.110s 392.890us 60 60 100.00
hmac_test_hmac512_vectors 19.450s 1675.440us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 45.040s 3038.664us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 622.810s 3869.469us 10 10 100.00
error 10 10 100.00
hmac_error 80.100s 4586.499us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 103.490s 7121.741us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.990s 2808.386us 10 10 100.00
hmac_long_msg 79.890s 8963.499us 10 10 100.00
hmac_back_pressure 78.680s 1437.739us 25 25 100.00
hmac_datapath_stress 622.810s 3869.469us 10 10 100.00
hmac_burst_wr 45.040s 3038.664us 50 50 100.00
hmac_stress_all 2122.210s 56470.055us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.990s 2808.386us 10 10 100.00
hmac_long_msg 79.890s 8963.499us 10 10 100.00
hmac_back_pressure 78.680s 1437.739us 25 25 100.00
hmac_datapath_stress 622.810s 3869.469us 10 10 100.00
hmac_wipe_secret 103.490s 7121.741us 10 10 100.00
hmac_test_sha256_vectors 261.390s 18411.647us 30 30 100.00
hmac_test_sha384_vectors 596.290s 13998.807us 75 75 100.00
hmac_test_sha512_vectors 537.720s 15762.297us 75 75 100.00
hmac_test_hmac256_vectors 16.040s 356.388us 50 50 100.00
hmac_test_hmac384_vectors 18.110s 392.890us 60 60 100.00
hmac_test_hmac512_vectors 19.450s 1675.440us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.990s 2808.386us 10 10 100.00
hmac_long_msg 79.890s 8963.499us 10 10 100.00
hmac_back_pressure 78.680s 1437.739us 25 25 100.00
hmac_datapath_stress 622.810s 3869.469us 10 10 100.00
hmac_burst_wr 45.040s 3038.664us 50 50 100.00
hmac_error 80.100s 4586.499us 10 10 100.00
hmac_wipe_secret 103.490s 7121.741us 10 10 100.00
hmac_test_sha256_vectors 261.390s 18411.647us 30 30 100.00
hmac_test_sha384_vectors 596.290s 13998.807us 75 75 100.00
hmac_test_sha512_vectors 537.720s 15762.297us 75 75 100.00
hmac_test_hmac256_vectors 16.040s 356.388us 50 50 100.00
hmac_test_hmac384_vectors 18.110s 392.890us 60 60 100.00
hmac_test_hmac512_vectors 19.450s 1675.440us 75 75 100.00
hmac_stress_all 2122.210s 56470.055us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2122.210s 56470.055us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 26.245us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.960s 16.982us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.560s 1114.506us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.560s 1114.506us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.340s 68.592us 5 5 100.00
hmac_csr_rw 1.290s 105.350us 20 20 100.00
hmac_csr_aliasing 8.980s 3426.619us 5 5 100.00
hmac_same_csr_outstanding 2.890s 1285.868us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.340s 68.592us 5 5 100.00
hmac_csr_rw 1.290s 105.350us 20 20 100.00
hmac_csr_aliasing 8.980s 3426.619us 5 5 100.00
hmac_same_csr_outstanding 2.890s 1285.868us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.460s 103.479us 5 5 100.00
hmac_tl_intg_err 4.470s 2269.835us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.470s 2269.835us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.990s 2808.386us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.590s 138.420us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 472.430s 6490.536us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.700s 41.470us 1 1 100.00

Error Messages

   Test seed line log context