Simulation Results: keymgr

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.96 %
  • code
  • 98.94 %
  • assert
  • 97.72 %
  • func
  • 91.21 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 98.18 %
  • toggle
  • 98.37 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.76%
V2S
100.00%
V3
62.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 21.050s 2415.902us 50 50 100.00
random 50 50 100.00
keymgr_random 34.940s 6863.707us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.730s 30.103us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 2.080s 153.497us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 11.180s 3153.546us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 12.860s 529.318us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.630s 189.411us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 2.080s 153.497us 20 20 100.00
keymgr_csr_aliasing 12.860s 529.318us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 89.880s 8431.602us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 31.380s 1292.660us 50 50 100.00
keymgr_sideload_kmac 51.340s 6640.483us 50 50 100.00
keymgr_sideload_aes 33.550s 10914.346us 50 50 100.00
keymgr_sideload_otbn 32.090s 1788.954us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 21.630s 3516.159us 50 50 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 15.380s 1438.738us 50 50 100.00
kmac_error_response 49 50 98.00
keymgr_kmac_rsp_err 7.170s 331.125us 49 50 98.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 48.690s 7410.558us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 36.660s 2012.348us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 27.340s 2377.597us 50 50 100.00
stress_all 49 50 98.00
keymgr_stress_all 94.960s 16941.843us 49 50 98.00
intr_test 50 50 100.00
keymgr_intr_test 1.200s 170.795us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.360s 44.591us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.730s 129.052us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.730s 129.052us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.730s 30.103us 5 5 100.00
keymgr_csr_rw 2.080s 153.497us 20 20 100.00
keymgr_csr_aliasing 12.860s 529.318us 5 5 100.00
keymgr_same_csr_outstanding 3.210s 84.076us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.730s 30.103us 5 5 100.00
keymgr_csr_rw 2.080s 153.497us 20 20 100.00
keymgr_csr_aliasing 12.860s 529.318us 5 5 100.00
keymgr_same_csr_outstanding 3.210s 84.076us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 9.630s 260.061us 20 20 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.290s 475.211us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.290s 475.211us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.290s 475.211us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.290s 475.211us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.970s 1146.687us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 9.630s 260.061us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.290s 475.211us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 89.880s 8431.602us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 2.080s 153.497us 20 20 100.00
keymgr_random 34.940s 6863.707us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 2.080s 153.497us 20 20 100.00
keymgr_random 34.940s 6863.707us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 2.080s 153.497us 20 20 100.00
keymgr_random 34.940s 6863.707us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 15.380s 1438.738us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 36.660s 2012.348us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 36.660s 2012.348us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 34.940s 6863.707us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 22.720s 3035.556us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 27.700s 1508.935us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 15.380s 1438.738us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.700s 1508.935us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.700s 1508.935us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 27.700s 1508.935us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.210s 3163.364us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 27.700s 1508.935us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 31 50 62.00
keymgr_stress_all_with_rand_reset 23.350s 6153.697us 31 50 62.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 73792448867272896417229721855430764826786226861880645549257536105685593562345 786
UVM_ERROR @ 736789549 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 736789549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 53491961169396543793910669734391995241026013963184640857499457574076600588884 129
UVM_ERROR @ 146904065 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 146904065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 96874655022649354938299840645506667744909731743641284742841657032199840152413 145
UVM_ERROR @ 123978330 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123978330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 83705357152715787127208250269241418155123245835658487420572115549839893626174 391
UVM_ERROR @ 572237019 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 572237019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 16104802862634482184125480254153400465995420517839415926282171051714860533045 216
UVM_ERROR @ 268760974 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 268760974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 102003237028654537624604520871402775907021072276667486784738323063000080467335 1021
UVM_ERROR @ 519468546 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 519468546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 88843643540679574107297116391296710006487938012444511935532617410754651484963 209
UVM_ERROR @ 449077441 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 449077441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 94453796771826625048893463180591864138171124719097035969549501777221078461303 160
UVM_ERROR @ 221188406 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 221188406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 55526615933679118218810922067472053703302057726955999989724502638252151108685 150
UVM_ERROR @ 164181549 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 164181549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18961340812700728517397730661473862872491860168479153344629966814251534488319 194
UVM_ERROR @ 122210339 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 122210339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87517588984053680711754201015250761915426171446183572797293879329202144616366 213
UVM_ERROR @ 112889198 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 112889198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95398674471364233080421802562199112457720423133858392559205648288046900526039 591
UVM_ERROR @ 605433334 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 605433334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 100447589344120381465621805606102527886139003266491561017287474168439792711069 626
UVM_ERROR @ 288416915 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 288416915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 75997339066882023472679409989378732463347044328658687620422345755838045693291 1100
UVM_ERROR @ 376783078 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 376783078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 58385330838139532284745437090301381573851645750099597538668149445422531951966 124
UVM_ERROR @ 718839395 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 718839395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 86351022838564061654413472493681307983768756647669800442991568264521686166823 246
UVM_ERROR @ 845480579 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 845480579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 56746694594113447690133068421978432730729798568578489938096304354563517242273 150
UVM_ERROR @ 433189515 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 433189515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 378011781524491822858355021339637211909601090726039375259976344673678932364 100
UVM_ERROR @ 126586119 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 126586119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 30607894114381768484820328397282917113889141725543459631454728526181117524276 361
UVM_ERROR @ 126014503 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 126014503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
keymgr_kmac_rsp_err 60644992567335913706361831081354287762537464795126313659043974676365309199821 226
UVM_ERROR @ 331124896 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 331124896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Sealing Kmac
keymgr_stress_all 27556142703758073705839140590020055280979517817564404735899816678105012059964 965
UVM_ERROR @ 2023848463 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (13380134947743349549829372903825346253490733089390131046243250590445503277727852513813268284043432657690135778273794409861319493127821010355556376600756177 [0xff78bcbe6c5cf46d9ef4ac1718a1b294f0729e952f53b302beaa7cdd44f70dddba048f53d27b772655663be2021fb15a78d40cdf986e41ae412fb380ecf1bfd1] vs 13380134947743349549829372903825346253490733089390131046243250590445503277727852513813268284043432657690135778273794409861319493127821010355556376600756177 [0xff78bcbe6c5cf46d9ef4ac1718a1b294f0729e952f53b302beaa7cdd44f70dddba048f53d27b772655663be2021fb15a78d40cdf986e41ae412fb380ecf1bfd1]) KMAC key at state StDisabled for Sealing Kmac
UVM_INFO @ 2023848463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---