| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| keymgr_dpe_smoke | 197.180s | 19747.068us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.270s | 56.635us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| keymgr_dpe_csr_rw | 1.130s | 47.860us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 11.920s | 3012.449us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 6.070s | 1076.180us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 1.660s | 52.805us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| keymgr_dpe_csr_rw | 1.130s | 47.860us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 6.070s | 1076.180us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 50 | 50 | 100.00 | |||
| keymgr_dpe_intr_test | 1.070s | 17.362us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| keymgr_dpe_alert_test | 1.440s | 73.060us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| keymgr_dpe_tl_errors | 2.620s | 1519.321us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| keymgr_dpe_tl_errors | 2.620s | 1519.321us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.270s | 56.635us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_rw | 1.130s | 47.860us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 6.070s | 1076.180us | 5 | 5 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.400s | 300.622us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.270s | 56.635us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_rw | 1.130s | 47.860us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 6.070s | 1076.180us | 5 | 5 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.400s | 300.622us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| keymgr_dpe_tl_intg_err | 4.610s | 701.197us | 20 | 20 | 100.00 | |
| keymgr_dpe_sec_cm | 13.830s | 1144.948us | 5 | 5 | 100.00 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.590s | 121.164us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.590s | 121.164us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.590s | 121.164us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.590s | 121.164us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 6.420s | 269.843us | 20 | 20 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 13.830s | 1144.948us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 13.830s | 1144.948us | 5 | 5 | 100.00 | |
| Test | seed | line | log context |
|---|