Simulation Results: kmac

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.67 %
  • code
  • 94.32 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.20 %
  • branch
  • 97.08 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 89.470s 16369.068us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.280s 22.647us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.410s 50.288us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 15.770s 3203.651us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.040s 1056.925us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.690s 92.943us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.410s 50.288us 20 20 100.00
kmac_csr_aliasing 7.040s 1056.925us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.140s 64.313us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.900s 21.555us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3729.070s 269464.760us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1330.150s 37666.341us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2062.790s 208893.580us 5 5 100.00
kmac_test_vectors_sha3_256 1964.880s 87008.253us 5 5 100.00
kmac_test_vectors_sha3_384 1489.540s 44912.823us 5 5 100.00
kmac_test_vectors_sha3_512 1082.360s 147601.493us 5 5 100.00
kmac_test_vectors_shake_128 2293.820s 303021.571us 5 5 100.00
kmac_test_vectors_shake_256 1665.150s 227693.256us 5 5 100.00
kmac_test_vectors_kmac 3.900s 408.503us 5 5 100.00
kmac_test_vectors_kmac_xof 3.470s 386.483us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 478.660s 329349.854us 50 50 100.00
app 50 50 100.00
kmac_app 368.000s 49658.812us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 357.970s 16423.260us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 372.040s 51086.916us 50 50 100.00
error 50 50 100.00
kmac_error 483.290s 82515.805us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 20.040s 7985.638us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.940s 1543.157us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 39.180s 6621.871us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 37.820s 19399.954us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 49.840s 19961.400us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 27.430s 1070.711us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3712.840s 1850686.070us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.100s 59.860us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.310s 303.023us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.350s 258.055us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.350s 258.055us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.280s 22.647us 5 5 100.00
kmac_csr_rw 1.410s 50.288us 20 20 100.00
kmac_csr_aliasing 7.040s 1056.925us 5 5 100.00
kmac_same_csr_outstanding 2.330s 133.211us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.280s 22.647us 5 5 100.00
kmac_csr_rw 1.410s 50.288us 20 20 100.00
kmac_csr_aliasing 7.040s 1056.925us 5 5 100.00
kmac_same_csr_outstanding 2.330s 133.211us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.750s 85.764us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.750s 85.764us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.750s 85.764us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.750s 85.764us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.300s 92.967us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.460s 265.762us 20 20 100.00
kmac_sec_cm 107.590s 33743.481us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.460s 265.762us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 27.430s 1070.711us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 89.470s 16369.068us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 478.660s 329349.854us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.750s 85.764us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 107.590s 33743.481us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 107.590s 33743.481us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 107.590s 33743.481us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 89.470s 16369.068us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 27.430s 1070.711us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 107.590s 33743.481us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 358.620s 36875.008us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 89.470s 16369.068us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 178.210s 3494.559us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 56489514052562737915649408931156706017756083558547593817020823472038710926966 333
UVM_ERROR @ 3824893305 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3824893305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---