Simulation Results: kmac

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.34 %
  • code
  • 92.17 %
  • assert
  • 97.74 %
  • func
  • 96.12 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.69%
V2S
99.80%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 88.460s 51321.501us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.450s 121.801us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.410s 113.023us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.660s 3136.066us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.610s 1796.897us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.620s 88.281us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.410s 113.023us 20 20 100.00
kmac_csr_aliasing 7.610s 1796.897us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.030s 16.466us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.680s 115.711us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3324.610s 119819.781us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 833.270s 34476.329us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1932.290s 93496.704us 5 5 100.00
kmac_test_vectors_sha3_256 1811.960s 59499.130us 5 5 100.00
kmac_test_vectors_sha3_384 1468.690s 334635.813us 5 5 100.00
kmac_test_vectors_sha3_512 1043.320s 147932.825us 5 5 100.00
kmac_test_vectors_shake_128 1941.040s 186364.857us 5 5 100.00
kmac_test_vectors_shake_256 2180.720s 381180.878us 5 5 100.00
kmac_test_vectors_kmac 2.840s 270.195us 5 5 100.00
kmac_test_vectors_kmac_xof 2.540s 48.089us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 395.140s 176301.029us 50 50 100.00
app 50 50 100.00
kmac_app 344.760s 19976.666us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 282.220s 316541.638us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 313.070s 71320.117us 50 50 100.00
error 49 50 98.00
kmac_error 331.990s 26273.869us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 13.580s 6146.609us 50 50 100.00
sideload_invalid 40 50 80.00
kmac_sideload_invalid 141.840s 10206.358us 40 50 80.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 32.300s 5523.178us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 38.900s 1607.979us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 78.660s 87803.871us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 22.750s 4312.448us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2172.070s 86240.266us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.130s 16.845us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.230s 146.245us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.360s 156.262us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.360s 156.262us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.450s 121.801us 5 5 100.00
kmac_csr_rw 1.410s 113.023us 20 20 100.00
kmac_csr_aliasing 7.610s 1796.897us 5 5 100.00
kmac_same_csr_outstanding 2.980s 127.536us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.450s 121.801us 5 5 100.00
kmac_csr_rw 1.410s 113.023us 20 20 100.00
kmac_csr_aliasing 7.610s 1796.897us 5 5 100.00
kmac_same_csr_outstanding 2.980s 127.536us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.440s 288.508us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.440s 288.508us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.440s 288.508us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.440s 288.508us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 4.720s 958.419us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.790s 3229.865us 20 20 100.00
kmac_sec_cm 81.800s 39887.797us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.790s 3229.865us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 22.750s 4312.448us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 88.460s 51321.501us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 395.140s 176301.029us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.440s 288.508us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 81.800s 39887.797us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 81.800s 39887.797us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 81.800s 39887.797us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 88.460s 51321.501us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 22.750s 4312.448us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 81.800s 39887.797us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 362.960s 63949.418us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 88.460s 51321.501us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
kmac_stress_all_with_rand_reset 261.240s 18205.185us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 84928825912603054359943144409263380646998175883291194830320620884472468256938 191
UVM_ERROR @ 81208531 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1358916991 [0x50ff6d7f] vs 2761239473 [0xa4952bb1]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
UVM_INFO @ 81208531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 13064586563954713844447151219545235499339326470068850779745483068695712919589 203
UVM_ERROR @ 2385050820 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2385050820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 15361543283159988319101541632092949520428227342257255476263048612181312261104 125
UVM_ERROR @ 1777528231 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1777528231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 84918467922242794597975073284437309271889576722748337405211065397882030853400 94
UVM_ERROR @ 1532640070 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1532640070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)
kmac_sideload_invalid 99929121912835145443326314790297897536244153022818318849545751660975087418236 95
UVM_FATAL @ 10508859375 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x77376000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10508859375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 39704749349550859915484309366249559369643617154643435824691388805677390942411 75
UVM_FATAL @ 10009210441 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfc379000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10009210441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 12562465107459239225556552719161331734428737874846367709337304661502049845083 75
UVM_FATAL @ 10009918230 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4fba000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10009918230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 77420456564460870182929002747866445840542960763953808152997654608364993461774 75
UVM_FATAL @ 10012317834 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x72a02000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10012317834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 6927844312271011267045337905116474696573222255233366767890107289859588158516 75
UVM_FATAL @ 10018154344 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x871ba000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10018154344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 64614934295779365773217095194600956496130156039337063485540420136702640111351 342
UVM_ERROR @ 3872914564 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3872914564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 73994910638511974267796517857392122843742198395662940165164757513690293082521 82
UVM_FATAL @ 10093088070 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x13a09000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10093088070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 11272469462460131337256903783652658778861197412495157277522989749008698083597 243
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 113421197405233768230406501892810245741229416446099728780047590131280931468513 85
UVM_FATAL @ 10358293371 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6887d000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10358293371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 101280946630879060566663394311724488588828487037511811012796821734379988137693 82
UVM_FATAL @ 10174411043 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9a0d2000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10174411043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 25941741623727917447477710495459976320229429771321707681642454441785855253942 77
UVM_FATAL @ 10158539108 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa00e8000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10158539108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33)
kmac_sideload_invalid 68432890057683724842144391327750271985788299408723854007973977990547544708960 110
UVM_FATAL @ 10206357790 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe70be000, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
UVM_INFO @ 10206357790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---