Simulation Results: mbx

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.65 %
  • code
  • 91.80 %
  • assert
  • 97.01 %
  • func
  • 86.13 %
  • block
  • 96.88 %
  • line
  • 96.86 %
  • branch
  • 92.43 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
98.41%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 2 2 100.00
mbx_smoke 47.000s 14101.112us 2 2 100.00
csr_hw_reset 5 5 100.00
mbx_csr_hw_reset 2.000s 39.707us 5 5 100.00
csr_rw 20 20 100.00
mbx_csr_rw 2.000s 22.148us 20 20 100.00
csr_bit_bash 5 5 100.00
mbx_csr_bit_bash 5.000s 849.133us 5 5 100.00
csr_aliasing 5 5 100.00
mbx_csr_aliasing 2.000s 28.832us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
mbx_csr_mem_rw_with_rand_reset 3.000s 68.457us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
mbx_csr_rw 2.000s 22.148us 20 20 100.00
mbx_csr_aliasing 2.000s 28.832us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 2 50.00
mbx_stress 108.000s 8539.585us 1 2 50.00
mbx_max_activity 0 2 0.00
mbx_stress_zero_delays 7.000s 349.545us 0 2 0.00
mbx_imbx_oob 1 2 50.00
mbx_imbx_oob 15.000s 4908.191us 1 2 50.00
mbx_doe_intr_msg 5 5 100.00
mbx_doe_intr_msg 24.000s 2239.636us 5 5 100.00
alert_test 50 50 100.00
mbx_alert_test 2.000s 24.083us 50 50 100.00
intr_test 50 50 100.00
mbx_intr_test 2.000s 13.149us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
mbx_tl_errors 5.000s 99.667us 20 20 100.00
tl_d_illegal_access 20 20 100.00
mbx_tl_errors 5.000s 99.667us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
mbx_csr_hw_reset 2.000s 39.707us 5 5 100.00
mbx_csr_rw 2.000s 22.148us 20 20 100.00
mbx_csr_aliasing 2.000s 28.832us 5 5 100.00
mbx_same_csr_outstanding 2.000s 34.887us 20 20 100.00
tl_d_partial_access 50 50 100.00
mbx_csr_hw_reset 2.000s 39.707us 5 5 100.00
mbx_csr_rw 2.000s 22.148us 20 20 100.00
mbx_csr_aliasing 2.000s 28.832us 5 5 100.00
mbx_same_csr_outstanding 2.000s 34.887us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
mbx_sec_cm 2.000s 34.320us 5 5 100.00
mbx_tl_intg_err 8.000s 1545.734us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 7245510023151902114660458450262389985664363415073652742303254434717869568653 315
UVM_ERROR @ 349544515 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 349544515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 92963573503759457814274264771485144414916623712862387096786560561347589967833 86
UVM_ERROR @ 25198349 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 25198349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress 41872790671363855155111329329595012149182226440599177275325607893345232421855 660
UVM_ERROR @ 1780887535 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 1780887535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress_zero_delays 79250217934735005411778603581463155885906714544661889937996419701593324293686 348
UVM_ERROR @ 1206529086 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (908956960 [0x362d9520] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 1206529086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---