Simulation Results: otbn

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.87 %
  • code
  • 97.00 %
  • assert
  • 96.61 %
  • func
  • 100.00 %
  • block
  • 99.58 %
  • line
  • 99.68 %
  • branch
  • 95.06 %
  • toggle
  • 93.24 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.42%
V2S
95.75%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 13.000s 242.811us 1 1 100.00
single_binary 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 4.000s 19.062us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 6.000s 24.327us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 7.000s 28.024us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 4.000s 53.286us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 61.291us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 6.000s 24.327us 20 20 100.00
otbn_csr_aliasing 4.000s 53.286us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 51.000s 1861.760us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 21.000s 1966.954us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 37.000s 592.114us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 54.000s 519.031us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 95.000s 3249.670us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 74.000s 204.994us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 75.000s 291.786us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 62.682us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 24.000s 50.510us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 6.000s 22.471us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 7.000s 27.685us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 7.000s 233.180us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 7.000s 233.180us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 4.000s 19.062us 5 5 100.00
otbn_csr_rw 6.000s 24.327us 20 20 100.00
otbn_csr_aliasing 4.000s 53.286us 5 5 100.00
otbn_same_csr_outstanding 5.000s 59.175us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 4.000s 19.062us 5 5 100.00
otbn_csr_rw 6.000s 24.327us 20 20 100.00
otbn_csr_aliasing 4.000s 53.286us 5 5 100.00
otbn_same_csr_outstanding 5.000s 59.175us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 23.000s 80.501us 10 10 100.00
otbn_dmem_err 38.000s 589.525us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 18.000s 85.973us 5 5 100.00
otbn_controller_ispr_rdata_err 40.000s 561.129us 5 5 100.00
otbn_mac_bignum_acc_err 28.000s 186.327us 5 5 100.00
otbn_urnd_err 7.000s 185.590us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 8.000s 208.758us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 6.000s 20.098us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 8.000s 36.886us 8 10 80.00
tl_intg_err 22 25 88.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
otbn_tl_intg_err 34.000s 225.219us 20 20 100.00
passthru_mem_tl_intg_err 15 20 75.00
otbn_passthru_mem_tl_intg_err 44.000s 533.190us 15 20 75.00
prim_fsm_check 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
prim_count_check 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 242.811us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 38.000s 589.525us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 23.000s 80.501us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 34.000s 225.219us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 75.000s 291.786us 58 60 96.67
sec_cm_controller_fsm_local_esc 37 40 92.50
otbn_imem_err 23.000s 80.501us 10 10 100.00
otbn_dmem_err 38.000s 589.525us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 62.682us 5 5 100.00
otbn_illegal_mem_acc 8.000s 208.758us 5 5 100.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_controller_fsm_sparse 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 37 40 92.50
otbn_imem_err 23.000s 80.501us 10 10 100.00
otbn_dmem_err 38.000s 589.525us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 62.682us 5 5 100.00
otbn_illegal_mem_acc 8.000s 208.758us 5 5 100.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_scramble_ctrl_fsm_sparse 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 75.000s 291.786us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 37 40 92.50
otbn_imem_err 23.000s 80.501us 10 10 100.00
otbn_dmem_err 38.000s 589.525us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 62.682us 5 5 100.00
otbn_illegal_mem_acc 8.000s 208.758us 5 5 100.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_start_stop_ctrl_fsm_sparse 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 49.351us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 13.000s 43.180us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 51.000s 245.517us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 51.000s 245.517us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 37.506us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_stack_wr_ptr_ctr_redun 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 12.000s 241.750us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_loop_stack_ctr_redun 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 10.000s 95.275us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 10.000s 95.275us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 4 7 57.14
otbn_sec_wipe_err 16.000s 32.265us 4 7 57.14
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 95.000s 3249.670us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 19.000s 207.427us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 89.000s 755.653us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 2 5 40.00
otbn_sec_cm 215.000s 1207.490us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
otbn_stress_all_with_rand_reset 350.000s 2808.904us 8 10 80.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 109657049240211287147781886434991531086500531154606295160643294069003542742285 122
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 114064674 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 114064674 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 114064674 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 114064674 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 114064674 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 60932918990477769408121046284408764992612663542144198462851421076695409079798 116
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 371080254 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 371080254 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 371080254 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 371080254 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 371080254 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 95000654538046464048380114550040359187376624540121502560318549510324750799365 103
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 82842024 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 82842024 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 82842024 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 82842024 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 82842024 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sec_wipe_err 41312684002482157069687568245563237207807833972826295125754776428550789818065 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 47715248 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 47715248 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 47715248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 62329740030646687799399282449746006022008189327947087597952882685187006374805 108
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13780649 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 13780649 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13780649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 75012833542485862596505618979346469443771440534040087370294059223068316004975 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 32265132 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 32265132 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 32265132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed
otbn_partial_wipe 75728874567916027705894681511159722839902296883055449901639874887440337968972 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 8093492 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
UVM_ERROR @ 8093492 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 8093492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 23912004178234647393747874407055605516976441643363480961825895970572732328968 156
UVM_FATAL @ 21901515 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 21901515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 65673133323343328366867786857237150569576571539860783923379961203424362160355 105
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 18258552 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 18258552 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 18258552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 8838303297177593027333689878975008540207340190729525498866510839428121225158 186
UVM_ERROR @ 926136383 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 926136383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 71707832332469226812795403588033274652740566180055000169660728374902278544103 110
UVM_ERROR @ 3719647 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 3719647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 92949250031191166258462211639098534619992555344079278355286945994830172245098 109
UVM_ERROR @ 6517309 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 6517309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 22736837453124822080523593301166388078515069463411041868276939483662571460729 118
UVM_FATAL @ 122415883 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 122415883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 35651929628340350343652989382379090118272969801995682069922689448444999370000 83
UVM_FATAL @ 1450848 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1450848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 65718848337724409357600708248117266914083471135846335898312703522030727096374 88
UVM_FATAL @ 22247549 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 22247549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 14287071956805485214432372365586268031438668415342820020218775194965967307306 113
UVM_FATAL @ 68169637 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 68169637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 33797081231417660835129016499217413369609939064217453730111354058731120575027 88
UVM_FATAL @ 97000762 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 97000762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---