Simulation Results: rom_ctrl

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 99.45 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.51 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.05%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.690s 409.419us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 8.560s 179.825us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.420s 549.557us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.440s 174.701us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.200s 299.352us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.300s 576.310us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.420s 549.557us 20 20 100.00
rom_ctrl_csr_aliasing 6.200s 299.352us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 7.080s 172.748us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 4.890s 264.558us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.650s 185.447us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 22.570s 727.772us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.160s 225.647us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 6.970s 531.986us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 11.420s 262.765us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 11.420s 262.765us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.560s 179.825us 5 5 100.00
rom_ctrl_csr_rw 6.420s 549.557us 20 20 100.00
rom_ctrl_csr_aliasing 6.200s 299.352us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.280s 137.216us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.560s 179.825us 5 5 100.00
rom_ctrl_csr_rw 6.420s 549.557us 20 20 100.00
rom_ctrl_csr_aliasing 6.200s 299.352us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.280s 137.216us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.710s 1655.037us 20 20 100.00
tl_intg_err 22 25 88.00
rom_ctrl_tl_intg_err 54.890s 283.066us 20 20 100.00
rom_ctrl_sec_cm 213.400s 581.102us 2 5 40.00
prim_fsm_check 2 5 40.00
rom_ctrl_sec_cm 213.400s 581.102us 2 5 40.00
prim_count_check 2 5 40.00
rom_ctrl_sec_cm 213.400s 581.102us 2 5 40.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_compare_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 213.400s 581.102us 2 5 40.00
sec_cm_fsm_sparse 2 5 40.00
rom_ctrl_sec_cm 213.400s 581.102us 2 5 40.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.690s 409.419us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.690s 409.419us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.690s 409.419us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 54.890s 283.066us 20 20 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
rom_ctrl_kmac_err_chk 7.160s 225.647us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 108.350s 9667.373us 18 20 90.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.710s 1655.037us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 213.400s 581.102us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 536.720s 16151.520us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 50623719555340914891645143481681195112248650516581429180525271021674743280790 168
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 20913888ps failed at 20913888ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 20933888ps failed at 20933888ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 1929913078217478883795195229156874954957363545222651345345861248025919606775 301
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 18081920ps failed at 18081920ps
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 18081920ps failed at 18081920ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 33176599766681088237650779299828145760180368843680320331359347933830663905128 238
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 177238440ps failed at 177238440ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 177238440ps failed at 177238440ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 14053724257339321010748221655425573722354662138108727957043279396456734844889 77
UVM_ERROR @ 192975779 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 192975779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 38468209832361696897474974437698490309117726914202464125342556947735941829651 94
UVM_ERROR @ 811845542 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 811845542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---