rom_ctrl Simulation Results

Simulation Results: rom_ctrl

19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.48 %

code
99.36 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.27 %

cond
98.07 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		92.45%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	10.810s	1886.417us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	16.240s	395.512us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	12.240s	289.009us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	12.000s	330.199us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	11.410s	526.578us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	16.810s	4015.653us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	12.240s	289.009us	20	20	100.00
	rom_ctrl_csr_aliasing	11.410s	526.578us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	15.280s	1074.926us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	10.110s	218.172us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	9.950s	557.228us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	45.930s	1289.980us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	23.880s	571.854us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	12.510s	287.231us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	15.230s	211.360us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	15.230s	211.360us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	16.240s	395.512us	5	5	100.00
	rom_ctrl_csr_rw	12.240s	289.009us	20	20	100.00
	rom_ctrl_csr_aliasing	11.410s	526.578us	5	5	100.00
	rom_ctrl_same_csr_outstanding	16.020s	2086.102us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	16.240s	395.512us	5	5	100.00
	rom_ctrl_csr_rw	12.240s	289.009us	20	20	100.00
	rom_ctrl_csr_aliasing	11.410s	526.578us	5	5	100.00
	rom_ctrl_same_csr_outstanding	16.020s	2086.102us	20	20	100.00

V2S

294/318 passed

92.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	62.360s	3207.216us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_sec_cm	562.680s	2519.304us	1	5	20.00
	rom_ctrl_tl_intg_err	137.420s	887.101us	20	20	100.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	562.680s	2519.304us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	562.680s	2519.304us	1	5	20.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	562.680s	2519.304us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	562.680s	2519.304us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	10.810s	1886.417us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	10.810s	1886.417us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	10.810s	1886.417us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	137.420s	887.101us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
	rom_ctrl_kmac_err_chk	23.880s	571.854us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	267.530s	7807.185us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	62.360s	3207.216us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	562.680s	2519.304us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	423.250s	32257.077us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	94644957039910554072024282520530993446575520897960601264729779078620664634038	108	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 15525467ps failed at 15525467ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 15525467ps failed at 15525467ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	89711199907019228195050267928055469270937879113169771253104852889967079944632	301	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 71346772ps failed at 71346772ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 71346772ps failed at 71346772ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	114580924097171586568606425138192357077635303414142062933350479472639587366677	237	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 61116557ps failed at 61116557ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 61116557ps failed at 61116557ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	74278266669296675816519665681582642110955530666969265683462905377478450615994	115	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 14989258ps failed at 14989258ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 24754884ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 24754884ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))