spi_host Simulation Results

Simulation Results: spi_host

19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.55 %

code
95.02 %

assert
95.21 %

func
90.42 %

block
96.82 %

line
98.69 %

branch
93.35 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.82%
V2S		100.00%
unmapped		90.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	93.000s	12693.650us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	33.808us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	23.884us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	4.000s	624.896us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	34.217us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	47.519us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	23.884us	20	20	100.00
	spi_host_csr_aliasing	2.000s	34.217us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	2.000s	15.427us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	1.000s	26.161us	5	5	100.00

1138/1140 passed

99.82 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	2.000s	24.480us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	22.000s	438.328us	50	50	100.00
	spi_host_error_cmd	2.000s	18.880us	50	50	100.00
	spi_host_event	787.000s	110153.519us	50	50	100.00
clock_rate				50	50	100.00
	spi_host_speed	10.000s	652.698us	50	50	100.00
speed				50	50	100.00
	spi_host_speed	10.000s	652.698us	50	50	100.00
chip_select_timing				50	50	100.00
	spi_host_speed	10.000s	652.698us	50	50	100.00
sw_reset				50	50	100.00
	spi_host_sw_reset	83.000s	6161.015us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	29.937us	50	50	100.00
cpol_cpha				50	50	100.00
	spi_host_speed	10.000s	652.698us	50	50	100.00
full_cycle				50	50	100.00
	spi_host_speed	10.000s	652.698us	50	50	100.00
duplex				50	50	100.00
	spi_host_smoke	93.000s	12693.650us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	93.000s	12693.650us	50	50	100.00
stress_all				50	50	100.00
	spi_host_stress_all	70.000s	2134.683us	50	50	100.00
spien				50	50	100.00
	spi_host_spien	261.000s	27943.950us	50	50	100.00
stall				48	50	96.00
	spi_host_status_stall	1109.000s	244175.368us	48	50	96.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	57.000s	2681.915us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	22.000s	438.328us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	49.283us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	19.753us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	3.000s	131.046us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	3.000s	131.046us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	33.808us	5	5	100.00
	spi_host_csr_rw	2.000s	23.884us	20	20	100.00
	spi_host_csr_aliasing	2.000s	34.217us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	53.891us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	33.808us	5	5	100.00
	spi_host_csr_rw	2.000s	23.884us	20	20	100.00
	spi_host_csr_aliasing	2.000s	34.217us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	53.891us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_sec_cm	2.000s	43.403us	5	5	100.00
	spi_host_tl_intg_err	3.000s	606.803us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	3.000s	606.803us	20	20	100.00

unmapped

9/10 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				9	10	90.00
	spi_host_upper_range_clkdiv	808.000s	45623.091us	9	10	90.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	spi_host_upper_range_clkdiv	36135170002825030173263352427731729279729661267537666113397542537168182711783	124	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	spi_host_status_stall	28434309875018016873070258540516458446993540335459336286294312195159977909894	811	UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
	spi_host_status_stall	38625958771993073286163085021338353250619192024113799603415459266508182117860	825	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 1342934018 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed UVM_ERROR @ 1342934018 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=1342934000 ps UVM_INFO @ 1342934018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---