Simulation Results: sram_ctrl

 
19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.71 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.14 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.59%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 100.910s 899.175us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.100s 26.429us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.060s 26.887us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.180s 268.163us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.050s 14.616us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.310s 3187.829us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.060s 26.887us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 14.616us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 355.710s 106472.756us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 161.960s 5895.666us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1277.220s 62958.271us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 452.260s 5970.002us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2866.050s 689619.003us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1133.000s 20416.352us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 109.040s 244690.011us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1301.600s 177713.164us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 109.250s 1349.786us 50 50 100.00
sram_ctrl_partial_access_b2b 611.730s 97551.101us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 91.510s 3054.449us 50 50 100.00
sram_ctrl_throughput_w_partial_write 103.200s 3133.559us 50 50 100.00
sram_ctrl_throughput_w_readback 109.740s 918.325us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1321.850s 53227.693us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.140s 1354.970us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 10622.580s 631373.245us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.060s 15.762us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.320s 146.025us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.320s 146.025us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.100s 26.429us 5 5 100.00
sram_ctrl_csr_rw 1.060s 26.887us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 14.616us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.210s 28.595us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.100s 26.429us 5 5 100.00
sram_ctrl_csr_rw 1.060s 26.887us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 14.616us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.210s 28.595us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 73.770s 29432.025us 19 20 95.00
tl_intg_err 19 25 76.00
sram_ctrl_sec_cm 1.090s 5.369us 0 5 0.00
sram_ctrl_tl_intg_err 4.670s 1995.689us 19 20 95.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.090s 5.369us 0 5 0.00
sec_cm_bus_integrity 19 20 95.00
sram_ctrl_tl_intg_err 4.670s 1995.689us 19 20 95.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1321.850s 53227.693us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1321.850s 53227.693us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.060s 26.887us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1301.600s 177713.164us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1301.600s 177713.164us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1301.600s 177713.164us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 109.040s 244690.011us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 46 50 92.00
sram_ctrl_mubi_enc_err 9.880s 3925.635us 46 50 92.00
sec_cm_mem_integrity 19 20 95.00
sram_ctrl_passthru_mem_tl_intg_err 73.770s 29432.025us 19 20 95.00
sec_cm_mem_readback 38 50 76.00
sram_ctrl_readback_err 9.430s 13199.572us 38 50 76.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 100.910s 899.175us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 100.910s 899.175us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1301.600s 177713.164us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.090s 5.369us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 109.040s 244690.011us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.090s 5.369us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.090s 5.369us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 100.910s 899.175us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.090s 5.369us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 141.790s 1205.344us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 4776131367362585644012353183099484738871967550017631123251820351885270657309 95
UVM_ERROR @ 667798477 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x66)
UVM_INFO @ 667798477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 69649694581173497786934192499035522899526284129835048605559882060599477266767 95
UVM_ERROR @ 698758847 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x38) != exp (0x4e)
UVM_INFO @ 698758847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 74684388591033404901612052405877559999634865883386116821772522111203853246608 95
UVM_ERROR @ 5996291706 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x20) != exp (0x5d)
UVM_INFO @ 5996291706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 98500381882004359903322000334680181680865570300369860050237474743348247967290 95
UVM_ERROR @ 2661691689 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x42) != exp (0x70)
UVM_INFO @ 2661691689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 30807171873046991792096918710926828669104181577758608570926299349637120560815 95
UVM_ERROR @ 2988116423 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x7d)
UVM_INFO @ 2988116423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 59597240728658225217450721355792496307790303028051233613281729392361634303830 95
UVM_ERROR @ 661502503 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x42) != exp (0x5d)
UVM_INFO @ 661502503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 19538436416612174919654973720714513445748478593620682977699520372145709728158 95
UVM_ERROR @ 5474447911 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x61) != exp (0xc)
UVM_INFO @ 5474447911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 101798475824653848580296156516396969122391003649367297457294990242336267344187 95
UVM_ERROR @ 678429074 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x7)
UVM_INFO @ 678429074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 30198084550555223238910903194395056085055350974532963754354409462042247627828 95
UVM_ERROR @ 2862376034 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6e) != exp (0x1)
UVM_INFO @ 2862376034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 57141494016174044109045517587804068300676013474542660754433229540303374374006 95
UVM_ERROR @ 673069461 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7f) != exp (0x17)
UVM_INFO @ 673069461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 52427757291953523324692800752194356307973484410783628240209825165824752434813 95
UVM_ERROR @ 675325534 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x5b)
UVM_INFO @ 675325534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 91950263591137867489978615760073402171640798585722860400932807588518806685962 95
UVM_ERROR @ 1435619943 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x48) != exp (0x51)
UVM_INFO @ 1435619943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 15878296676326060698578755233298172586751621472222008798604546620747529822607 97
UVM_ERROR @ 7119117 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7119117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 14802143071725118289392165544990066743565782648252548473449040696896969740104 96
UVM_ERROR @ 6537140 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6537140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 69557511898265367969824401789959943190466952063561476979360644867377137065764 96
UVM_ERROR @ 5701073 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5701073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 19814520776268825990057660610202072064815903989374521451084742808296632983502 96
UVM_ERROR @ 2071300 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2071300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 21491319078737268357864573216757318235727431503382592688292873517420650958324 99
UVM_ERROR @ 5368845 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5368845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 99146889715975358553458336696733730579551421279475770644691857972214734609892 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 796131858 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 796131858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 48744556891658782276737418951844983489359343413748456389103362790052631402952 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 701016398 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 701016398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 44013549788251715753882731051873877747316783310388927899933930036329665960480 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 682578392 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 682578392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 40106336693987247753165318915567569854286289239043041435793909223078771135296 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1344512450 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1344512450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
sram_ctrl_passthru_mem_tl_intg_err 65551569892057428658457182271088087138974226435695528477157555883180776546814 105
UVM_ERROR @ 5602185688 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 5602185688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_tl_intg_err 3154422853578962585838357602102203989864697081410152499090290147122659795835 186
UVM_ERROR @ 87497660 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 87497660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---