sram_ctrl Simulation Results

Simulation Results: sram_ctrl

19/12/2025 17:08:41 sha: cab660a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.75 %

code
96.12 %

assert
95.79 %

func
98.33 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		99.57%
V2		100.00%
V2S		94.23%
V3		98.00%

229/230 passed

99.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	107.220s	3080.564us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	0.920s	29.867us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	0.970s	12.959us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	2.820s	905.694us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.190s	256.201us	5	5	100.00
csr_mem_rw_with_rand_reset				19	20	95.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.350s	43.334us	19	20	95.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	0.970s	12.959us	20	20	100.00
	sram_ctrl_csr_aliasing	1.190s	256.201us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	13.660s	1338.234us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	7.480s	3626.486us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1717.770s	26165.370us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	342.580s	46258.235us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	91.470s	6493.560us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1255.290s	75395.403us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	12.260s	920.220us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1377.250s	17113.109us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	113.240s	3554.134us	50	50	100.00
	sram_ctrl_partial_access_b2b	669.710s	115544.743us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	104.360s	514.835us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	107.170s	609.560us	50	50	100.00
	sram_ctrl_throughput_w_readback	112.170s	1103.756us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1791.560s	43738.580us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.210s	44.292us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4260.540s	82087.144us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.060s	14.811us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.680s	595.965us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.680s	595.965us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.920s	29.867us	5	5	100.00
	sram_ctrl_csr_rw	0.970s	12.959us	20	20	100.00
	sram_ctrl_csr_aliasing	1.190s	256.201us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.120s	73.856us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.920s	29.867us	5	5	100.00
	sram_ctrl_csr_rw	0.970s	12.959us	20	20	100.00
	sram_ctrl_csr_aliasing	1.190s	256.201us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.120s	73.856us	20	20	100.00

V2S

735/780 passed

94.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.990s	383.349us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	1.120s	28.318us	0	5	0.00
	sram_ctrl_tl_intg_err	3.710s	357.147us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.120s	28.318us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	3.710s	357.147us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1791.560s	43738.580us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1791.560s	43738.580us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	0.970s	12.959us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1377.250s	17113.109us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1377.250s	17113.109us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1377.250s	17113.109us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	12.260s	920.220us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				47	50	94.00
	sram_ctrl_mubi_enc_err	1.560s	131.544us	47	50	94.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.990s	383.349us	20	20	100.00
sec_cm_mem_readback				38	50	76.00
	sram_ctrl_readback_err	1.450s	37.351us	38	50	76.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	107.220s	3080.564us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	107.220s	3080.564us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1377.250s	17113.109us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.120s	28.318us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	12.260s	920.220us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.120s	28.318us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.120s	28.318us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	107.220s	3080.564us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.120s	28.318us	0	5	0.00

49/50 passed

98.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				49	50	98.00
	sram_ctrl_stress_all_with_rand_reset	615.130s	3374.074us	49	50	98.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	77675997267305103413780188827342945760637656362181677692062798535476229355808	95	UVM_ERROR @ 86176487 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3) != exp (0x4) UVM_INFO @ 86176487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	73719642980578052010265756171284312459105523184497079194440471137723274984085	95	UVM_ERROR @ 99232357 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xf) != exp (0x1) UVM_INFO @ 99232357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	73930740717184277363393599224790447481206308620076421689730167222787806727805	95	UVM_ERROR @ 88231261 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2d) != exp (0x45) UVM_INFO @ 88231261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	43733721443061784410718103403984316234773704681862073336659013108508346584908	95	UVM_ERROR @ 58484498 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x13) != exp (0x16) UVM_INFO @ 58484498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	113836419373908202590906848915429795973960972387431287798874720076613496232043	95	UVM_ERROR @ 283958141 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3) != exp (0x51) UVM_INFO @ 283958141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	50660940231381952483735236145989834161135468717267962015896673210481230878081	95	UVM_ERROR @ 244287233 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x0) != exp (0x7d) UVM_INFO @ 244287233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	97130687362421348365959428301998484657412098228461390533426727465006314444256	95	UVM_ERROR @ 24938965 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x71) != exp (0xa) UVM_INFO @ 24938965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	52757721350451004846755534007080341593874391398624925762304296108643369822325	95	UVM_ERROR @ 526982161 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x64) != exp (0x7a) UVM_INFO @ 526982161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	86778634898720539108701408622299680946893859729587309481971198730112414416248	95	UVM_ERROR @ 26671463 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x28) != exp (0x20) UVM_INFO @ 26671463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	109417020858062185556543281178086520042563952361376307111701023418668891503825	95	UVM_ERROR @ 175038171 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x39) UVM_INFO @ 175038171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	63662931569135419384260389339251202679360127041119720556078453467236433795853	95	UVM_ERROR @ 94254817 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x25) != exp (0xa) UVM_INFO @ 94254817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	61519528609835805671524216001230185429219199409316163760320327645553616422462	96	UVM_ERROR @ 2571973 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 2571973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	68838382155743965865602972334097260000297049607530986063912434971168142355902	99	UVM_ERROR @ 6470196 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 6470196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	88538965163833709728340283153112247746749166000618068188200256264672865164770	100	UVM_ERROR @ 28318401 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 28318401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	34129912386180910472216935073564600215174720173321768086712145793283811107664	97	UVM_ERROR @ 2187011 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 2187011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
	sram_ctrl_sec_cm	109525267314465475217396881573208005399678459493853853028354772775527265496024	96	Offending '(!$isunknown(rdata_o))' UVM_ERROR @ 2651486 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 2651486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	22799747317217024219381521164785014675615465598706187718782749617573398763529	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 29746759 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 29746759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	2544112024267516115341153748656245134655094496237585519778604665820278808192	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 114094858 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 114094858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	54377197707202775221639133159961087535625003992453698822079524721182271373543	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 100485895 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 100485895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [sram_ctrl_readback_err_vseq] expect alert:fatal_error to fire
	sram_ctrl_readback_err	56316242301852766335227516448466515804776636518260309989904519270408719943905	95	UVM_ERROR @ 27562283 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_readback_err_vseq] expect alert:fatal_error to fire UVM_INFO @ 27562283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
	sram_ctrl_stress_all_with_rand_reset	74533300886110147862926103238822445349300301284367114211627575060311158284597	230	UVM_ERROR @ 2624456307 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 2624456307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	111473965818954436554297069944653454032630587422080796664007800514525534857475	101	UVM_ERROR @ 253498669 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 UVM_INFO @ 253498669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---