ac_range_check Simulation Results

Simulation Results: ac_range_check

26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.28 %

code
93.54 %

assert
97.63 %

func
58.67 %

block
99.21 %

line
99.94 %

branch
98.35 %

toggle
82.34 %

Validation stages

V1		100.00%
V2		96.46%
V2S		100.00%
V3		100.00%
unmapped		100.00%

120/120 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_smoke				20	20	100.00
	ac_range_check_smoke	59.000s	2689.595us	20	20	100.00
ac_range_check_smoke_racl				20	20	100.00
	ac_range_check_smoke_racl	78.000s	18632.379us	20	20	100.00
csr_hw_reset				5	5	100.00
	ac_range_check_csr_hw_reset	3.000s	37.367us	5	5	100.00
csr_rw				20	20	100.00
	ac_range_check_csr_rw	4.000s	51.877us	20	20	100.00
csr_bit_bash				5	5	100.00
	ac_range_check_csr_bit_bash	51.000s	4908.749us	5	5	100.00
csr_aliasing				5	5	100.00
	ac_range_check_csr_aliasing	35.000s	1848.899us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	ac_range_check_csr_mem_rw_with_rand_reset	4.000s	91.602us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	ac_range_check_csr_rw	4.000s	51.877us	20	20	100.00
	ac_range_check_csr_aliasing	35.000s	1848.899us	5	5	100.00

300/311 passed

96.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_lock_range				20	20	100.00
	ac_range_check_lock_range	24.000s	22.984us	20	20	100.00
ac_range_bypass_enable				1	1	100.00
	ac_range_check_bypass	65.000s	2843.438us	1	1	100.00
stress_all				39	50	78.00
	ac_range_check_stress_all	375.000s	11902.664us	39	50	78.00
alert_test				50	50	100.00
	ac_range_check_alert_test	3.000s	15.320us	50	50	100.00
intr_test				50	50	100.00
	ac_range_check_intr_test	2.000s	36.971us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	ac_range_check_tl_errors	6.000s	457.793us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	ac_range_check_tl_errors	6.000s	457.793us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	37.367us	5	5	100.00
	ac_range_check_csr_rw	4.000s	51.877us	20	20	100.00
	ac_range_check_csr_aliasing	35.000s	1848.899us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	722.011us	20	20	100.00
tl_d_partial_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	37.367us	5	5	100.00
	ac_range_check_csr_rw	4.000s	51.877us	20	20	100.00
	ac_range_check_csr_aliasing	35.000s	1848.899us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	722.011us	20	20	100.00

V2S

125/125 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	1188.462us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	1188.462us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	1188.462us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	ac_range_check_shadow_reg_errors	26.000s	1188.462us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	ac_range_check_shadow_reg_errors_with_csr_rw	125.000s	19606.308us	20	20	100.00
tl_intg_err				25	25	100.00
	ac_range_check_sec_cm	2.000s	35.627us	5	5	100.00
	ac_range_check_tl_intg_err	16.000s	605.333us	20	20	100.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	ac_range_check_stress_all_with_rand_reset	390.000s	3628.805us	50	50	100.00

unmapped

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				20	20	100.00
	ac_range_check_smoke_high_threshold	59.000s	3281.779us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: ac_range_check_reg_block.intr_state
	ac_range_check_stress_all	112403838209125271063441508707454220036603296281113262259821831662510846490618	13140	UVM_ERROR @ 11299875643 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 11299875643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	32440545498441668893260372017184876731246041499594967802960955879506056410334	4460	UVM_ERROR @ 6999692689 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 6999692689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	108410079600673866897248772649834488863555084111786260432303591005466265741820	8573	UVM_ERROR @ 2350428295 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2350428295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	56674502940569991685803491829071413645146238541518797856660149435412450202327	22496	UVM_ERROR @ 2627782502 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 2627782502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	9191854362519249577055675427868678717561428807272708973101331034887681365920	13194	UVM_ERROR @ 3053665406 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3053665406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	81710937315165191155101383346686299139471618087645881976733820181785059608985	8477	UVM_ERROR @ 3699916390 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3699916390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	45955870288441456985480345229359963351296490225430254997762034797312973798324	4676	UVM_ERROR @ 446496414 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 446496414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	2921720876466434929395425451905678779139804762320757711081330255192120995728	27439	UVM_ERROR @ 3097873717 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3097873717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	32989704810073220977453079713107529279225020007660145785219938699210380632331	17749	UVM_ERROR @ 3884147776 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3884147776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	19022831472829638471958668566425436346539606858501075617976521757376438167271	18429	UVM_ERROR @ 7624085547 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 7624085547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	93621067618172418670235394786407965090659907381816686914220950404868462202410	21316	UVM_ERROR @ 9730048101 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 9730048101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---