Simulation Results: aes

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.58 %
  • code
  • 92.94 %
  • assert
  • 98.40 %
  • func
  • 98.40 %
  • block
  • 96.23 %
  • line
  • 97.41 %
  • branch
  • 90.74 %
  • toggle
  • 97.99 %
  • FSM
  • 85.62 %
Validation stages
V1
100.00%
V2
99.77%
V2S
97.17%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 66.602us 1 1 100.00
smoke 50 50 100.00
aes_smoke 10.000s 451.972us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 88.126us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 95.395us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 7.000s 2224.956us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 4.000s 388.319us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 81.419us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 95.395us 20 20 100.00
aes_csr_aliasing 4.000s 388.319us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 10.000s 451.972us 50 50 100.00
aes_config_error 11.000s 433.137us 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
key_length 150 150 100.00
aes_smoke 10.000s 451.972us 50 50 100.00
aes_config_error 11.000s 433.137us 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
back2back 100 100 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
aes_b2b 33.000s 569.216us 50 50 100.00
backpressure 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
multi_message 199 200 99.50
aes_smoke 10.000s 451.972us 50 50 100.00
aes_config_error 11.000s 433.137us 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
aes_alert_reset 22.000s 2196.006us 49 50 98.00
failure_test 149 150 99.33
aes_man_cfg_err 4.000s 106.133us 50 50 100.00
aes_config_error 11.000s 433.137us 50 50 100.00
aes_alert_reset 22.000s 2196.006us 49 50 98.00
trigger_clear_test 50 50 100.00
aes_clear 16.000s 664.724us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 39.000s 9012.495us 1 1 100.00
reset_recovery 49 50 98.00
aes_alert_reset 22.000s 2196.006us 49 50 98.00
stress 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
sideload 100 100 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
aes_sideload 82.000s 4239.733us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 22.000s 3523.820us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 135.000s 25375.880us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 66.776us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 358.872us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 358.872us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 88.126us 5 5 100.00
aes_csr_rw 3.000s 95.395us 20 20 100.00
aes_csr_aliasing 4.000s 388.319us 5 5 100.00
aes_same_csr_outstanding 3.000s 92.924us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 88.126us 5 5 100.00
aes_csr_rw 3.000s 95.395us 20 20 100.00
aes_csr_aliasing 4.000s 388.319us 5 5 100.00
aes_same_csr_outstanding 3.000s 92.924us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 24.000s 2714.490us 50 50 100.00
fault_inject 676 700 96.57
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 453.871us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 453.871us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 453.871us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 453.871us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 1172.196us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 6.000s 1047.237us 5 5 100.00
aes_tl_intg_err 4.000s 628.503us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 628.503us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
aes_alert_reset 22.000s 2196.006us 49 50 98.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 453.871us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 453.871us 20 20 100.00
sec_cm_main_config_sparse 216 220 98.18
aes_smoke 10.000s 451.972us 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
aes_alert_reset 22.000s 2196.006us 49 50 98.00
aes_core_fi 43.000s 10044.699us 67 70 95.71
sec_cm_gcm_config_sparse 100 100 100.00
aes_config_error 11.000s 433.137us 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 453.871us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 5.000s 187.785us 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
aes_sideload 82.000s 4239.733us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 5.000s 187.785us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 5.000s 187.785us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 5.000s 187.785us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 5.000s 187.785us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 5.000s 187.785us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 10.000s 2590.795us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 35.000s 8310.908us 50 50 100.00
sec_cm_main_fsm_redun 726 750 96.80
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
aes_ctr_fi 3.000s 113.722us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 35.000s 8310.908us 50 50 100.00
sec_cm_cipher_fsm_redun 676 700 96.57
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
sec_cm_cipher_ctr_redun 344 350 98.29
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 35.000s 8310.908us 50 50 100.00
sec_cm_ctr_fsm_redun 382 400 95.50
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_ctr_fi 3.000s 113.722us 50 50 100.00
sec_cm_ctrl_sparse 726 750 96.80
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
aes_ctr_fi 3.000s 113.722us 50 50 100.00
sec_cm_main_fsm_global_esc 49 50 98.00
aes_alert_reset 22.000s 2196.006us 49 50 98.00
sec_cm_main_fsm_local_esc 726 750 96.80
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
aes_ctr_fi 3.000s 113.722us 50 50 100.00
sec_cm_cipher_fsm_local_esc 726 750 96.80
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
aes_ctr_fi 3.000s 113.722us 50 50 100.00
sec_cm_ctr_fsm_local_esc 382 400 95.50
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_ctr_fi 3.000s 113.722us 50 50 100.00
sec_cm_data_reg_local_esc 676 700 96.57
aes_fi 35.000s 8310.908us 50 50 100.00
aes_control_fi 57.000s 10008.705us 282 300 94.00
aes_cipher_fi 60.000s 10002.840us 344 350 98.29
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 33.000s 851.879us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 25534889050469642429627056793039904450964461683248303059744997000284303529651 431
UVM_ERROR @ 2260751102 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2260751102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 47821281804871370904126991972126462286181464687818406371118583284295927236869 307
UVM_ERROR @ 2434499533 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2434499533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 111637149581999933898454081528906402738818496338147194434684414525883543483614 601
UVM_ERROR @ 851878539 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 851878539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 6040814567941310604786562490762691115138092005643553525038406102948683082486 597
UVM_ERROR @ 1207202266 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1207202266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 52388792038613480889987205352298291712411884644614822792227733570414210407732 363
UVM_ERROR @ 908912902 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 908912902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 67095996657542195280961103373893280250215962720140077586640351622821193843654 234
UVM_ERROR @ 1413888552 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1413888552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 86691757172712850006184085031637181712627336830137220144822056304776896731468 284
UVM_FATAL @ 608721924 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 608721924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 65261791850722325750703460627110452722429089241114470765010324057813704349520 187
UVM_FATAL @ 554283903 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 554283903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 90376584970177125532199789218675071738026177384514844388222217374769741138893 857
UVM_FATAL @ 8447459225 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 8447459225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 32964708014921098861791800836072030945990256528424259572984002363369776504252 141
UVM_FATAL @ 10044699070 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10044699070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 59406101252899070492443868948044855137625981101291005439182377285641982143047 133
UVM_FATAL @ 10023951097 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10023951097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 37202875330814015371170439330322837252996370495239598758488046194229137171005 136
UVM_FATAL @ 10010026659 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010026659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 81339382770633911063431339935329863407616943468960776524729899410026136859603 507
UVM_FATAL @ 626410177 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 626410177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1129): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
aes_alert_reset 97751888812094599825738463793613536552285910782315716518527147408508960794940 606
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1129): (time 12262967 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 12250309 PS)
($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
|
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1135): (time 12262967 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 12250309 PS)
UVM_ERROR @ 12262967 ps: (aes_core.sv:1129) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 28401427535806850534357783561733749878976499598058973574732718423607848374021 133
UVM_FATAL @ 10005421466 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005421466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 39156513635076438815091961392122600607508437492121377186404478535269358548599 136
UVM_FATAL @ 10031386571 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10031386571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 32713878431486894092457705282152968574369883642596264187245971753647252051598 133
UVM_FATAL @ 10028456905 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10028456905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 10955317780115988822262820962768939236217584583836491477174500681287298505509 146
UVM_FATAL @ 10011126020 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011126020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 67539872999065486265012536589850611718687283504261799810465377917851634398306 147
UVM_FATAL @ 10032134492 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10032134492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 6988693667787745690108448042094166958687171370319537921421398602123270374738 148
UVM_FATAL @ 10006472839 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006472839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 99763104465362396554017310333695388896755194148641089143127230198054725280693 144
UVM_FATAL @ 10013232712 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013232712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 103016853451734585609683811536456763535594261401641523936372415361540710678027 150
UVM_FATAL @ 10008704653 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008704653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 2275152831560757598945366343166671419819151886778207343074146504065759445374 142
UVM_FATAL @ 10117307386 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10117307386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 114341811226479269337305242264667632824181459666945038400026198546656283236896 139
UVM_FATAL @ 10049702409 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10049702409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 69559401145786649311041113328310685983636022817427653781480130355971009290914 143
UVM_FATAL @ 10011381525 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011381525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 16660297897141516277601359453480107256396596881084480677941326874385296357515 141
UVM_FATAL @ 10002840444 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10002840444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 26991670968113289928599592343049059356318047900056661870416042134704115682509 138
UVM_FATAL @ 10019215992 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10019215992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 5580749840613259469628677800783941107067042331546900997788881629353893963162 141
UVM_FATAL @ 10008269880 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008269880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 91334438998781226721859470071618331377083836529305221168456836929651288546711 146
UVM_FATAL @ 10025150923 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10025150923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 72686659492252766539744925431803860424126091552436158503342607593943756182006 137
UVM_FATAL @ 10006892450 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006892450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
aes_control_fi 6706164664714254004505992385104198685757295820015903603623097055673449365238 None
Job timed out after 1 minutes
aes_control_fi 61616097096043081570213958836687895676501499390847020280454594904828130133617 None
Job timed out after 1 minutes
aes_control_fi 1616105682878482748746069348158383296120925240513354778357015657325192855956 None
Job timed out after 1 minutes
aes_control_fi 77591795211209325623003551863602745276070610393661098147042188385374855112552 None
Job timed out after 1 minutes
aes_cipher_fi 76194088483647689559982754268103577776554104759826346779351502245663117428555 None
Job timed out after 1 minutes
aes_control_fi 28810576563651838785636301937269352611700597051792964366496139540417973837281 None
Job timed out after 1 minutes
aes_control_fi 100184381216063940055273959972116571391784995861031891040652978952551613849321 None
Job timed out after 1 minutes
aes_control_fi 110024183117211161865586721767928094206050119592747441281183626503716896756865 None
Job timed out after 1 minutes