Simulation Results: csrng

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.51 %
  • code
  • 96.35 %
  • assert
  • 95.85 %
  • func
  • 91.32 %
  • block
  • 98.76 %
  • line
  • 99.64 %
  • branch
  • 96.88 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.81%
V2S
99.94%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 5.000s 162.465us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 2.000s 17.071us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 45.821us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 10.000s 244.286us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 8.000s 350.817us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 170.786us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 45.821us 20 20 100.00
csrng_csr_aliasing 8.000s 350.817us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
alerts 500 500 100.00
csrng_alert 51.000s 4875.025us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 110.815us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 349.000s 28753.973us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 349.000s 28753.973us 50 50 100.00
stress_all 47 50 94.00
csrng_stress_all 1924.000s 159279.919us 47 50 94.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 55.170us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 4.000s 47.070us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 23.000s 2513.668us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 23.000s 2513.668us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 2.000s 17.071us 5 5 100.00
csrng_csr_rw 3.000s 45.821us 20 20 100.00
csrng_csr_aliasing 8.000s 350.817us 5 5 100.00
csrng_same_csr_outstanding 6.000s 420.475us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 2.000s 17.071us 5 5 100.00
csrng_csr_rw 3.000s 45.821us 20 20 100.00
csrng_csr_aliasing 8.000s 350.817us 5 5 100.00
csrng_same_csr_outstanding 6.000s 420.475us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
csrng_tl_intg_err 13.000s 1546.574us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 3.000s 118.466us 50 50 100.00
csrng_csr_rw 3.000s 45.821us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 51.000s 4875.025us 500 500 100.00
sec_cm_intersig_mubi 47 50 94.00
csrng_stress_all 1924.000s 159279.919us 47 50 94.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 51.000s 4875.025us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
sec_cm_constants_lc_gated 47 50 94.00
csrng_stress_all 1924.000s 159279.919us 47 50 94.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 51.000s 4875.025us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 13.000s 1546.574us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
csrng_sec_cm 4.000s 402.199us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 16.000s 1044.906us 200 200 100.00
csrng_err 4.000s 110.815us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 732.000s 47255.111us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 59354930764438350619572410685996254851871094093532564941101286348445173714657 154
UVM_ERROR @ 36193525 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 36193525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 17146320053375236365138314768924273386210093803502202003049590724448219976952 144
UVM_ERROR @ 1430427892 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1430427892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 90348076791489831768184819782085807245157160444936418309244417804159392538223 145
UVM_ERROR @ 10014115 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 10014115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---