Simulation Results: dma

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.26 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 76.62 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 7.000s 708.236us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 8.000s 1410.750us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 8.000s 354.535us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 103.053us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 14.819us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 15.000s 1298.567us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 1154.680us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 29.141us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 14.819us 20 20 100.00
dma_csr_aliasing 7.000s 1154.680us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 57.000s 4145.456us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 810.000s 71837.845us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 243.000s 15392.716us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 243.000s 15392.716us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 810.000s 71837.845us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 416.000s 148687.444us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 243.000s 15392.716us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 14.000s 1862.362us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 206.000s 78294.935us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 189.379us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 39.366us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 136.048us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 136.048us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 103.053us 5 5 100.00
dma_csr_rw 2.000s 14.819us 20 20 100.00
dma_csr_aliasing 7.000s 1154.680us 5 5 100.00
dma_same_csr_outstanding 3.000s 106.165us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 103.053us 5 5 100.00
dma_csr_rw 2.000s 14.819us 20 20 100.00
dma_csr_aliasing 7.000s 1154.680us 5 5 100.00
dma_same_csr_outstanding 3.000s 106.165us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 24.000s 98.538us 5 5 100.00
dma_generic_stress 416.000s 148687.444us 5 5 100.00
dma_handshake_stress 243.000s 15392.716us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 11.000s 4450.512us 15 15 100.00
tl_intg_err 25 25 100.00
dma_tl_intg_err 4.000s 879.592us 20 20 100.00
dma_sec_cm 2.000s 17.821us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 179.000s 17193.610us 25 25 100.00
dma_longer_transfer 15.000s 694.781us 5 5 100.00
dma_stress_all_with_rand_reset 3.000s 1094.391us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 14137821763504790585679014774822180233332488658410086647863831700682520245059 91
UVM_ERROR @ 1094390954ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1094390954ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---