Simulation Results: edn

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.26 %
  • code
  • 95.51 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.430s 17.388us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.860s 15.755us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.150s 25.391us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.030s 871.930us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.290s 41.385us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.470s 61.007us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.150s 25.391us 20 20 100.00
edn_csr_aliasing 1.290s 41.385us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 53.770s 4476.950us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 53.770s 4476.950us 300 300 100.00
genbits 300 300 100.00
edn_genbits 53.770s 4476.950us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.590s 22.409us 50 50 100.00
alerts 200 200 100.00
edn_alert 2.130s 336.408us 200 200 100.00
errs 100 100 100.00
edn_err 1.680s 53.290us 100 100 100.00
disable 100 100 100.00
edn_disable 1.300s 18.105us 50 50 100.00
edn_disable_auto_req_mode 1.780s 47.727us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 6.590s 360.123us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.000s 15.306us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.450s 31.180us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.290s 642.534us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.290s 642.534us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.860s 15.755us 5 5 100.00
edn_csr_rw 1.150s 25.391us 20 20 100.00
edn_csr_aliasing 1.290s 41.385us 5 5 100.00
edn_same_csr_outstanding 1.380s 43.006us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.860s 15.755us 5 5 100.00
edn_csr_rw 1.150s 25.391us 20 20 100.00
edn_csr_aliasing 1.290s 41.385us 5 5 100.00
edn_same_csr_outstanding 1.380s 43.006us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.980s 182.936us 20 20 100.00
edn_sec_cm 8.730s 555.019us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.280s 57.726us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 2.130s 336.408us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.730s 555.019us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.730s 555.019us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.730s 555.019us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.730s 555.019us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 2.130s 336.408us 200 200 100.00
edn_sec_cm 8.730s 555.019us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 2.130s 336.408us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.980s 182.936us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 115.720s 18870.426us 50 50 100.00

Error Messages

   Test seed line log context