Simulation Results: edn

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.67 %
  • code
  • 94.64 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.85 %
  • toggle
  • 88.70 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.350s 20.369us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.870s 12.671us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.020s 109.700us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.030s 530.463us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.400s 130.422us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.330s 25.611us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.020s 109.700us 20 20 100.00
edn_csr_aliasing 1.400s 130.422us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 5.360s 519.879us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 5.360s 519.879us 300 300 100.00
genbits 300 300 100.00
edn_genbits 5.360s 519.879us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.530s 20.829us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.630s 38.046us 200 200 100.00
errs 100 100 100.00
edn_err 1.640s 29.900us 100 100 100.00
disable 100 100 100.00
edn_disable 1.240s 14.462us 50 50 100.00
edn_disable_auto_req_mode 1.880s 62.260us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 6.070s 801.745us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.940s 16.323us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 2.020s 148.350us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.920s 1258.701us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.920s 1258.701us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.870s 12.671us 5 5 100.00
edn_csr_rw 1.020s 109.700us 20 20 100.00
edn_csr_aliasing 1.400s 130.422us 5 5 100.00
edn_same_csr_outstanding 1.300s 35.369us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.870s 12.671us 5 5 100.00
edn_csr_rw 1.020s 109.700us 20 20 100.00
edn_csr_aliasing 1.400s 130.422us 5 5 100.00
edn_same_csr_outstanding 1.300s 35.369us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 5.740s 350.223us 5 5 100.00
edn_tl_intg_err 4.930s 1274.706us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.300s 19.042us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.630s 38.046us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.740s 350.223us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.740s 350.223us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.740s 350.223us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.740s 350.223us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.630s 38.046us 200 200 100.00
edn_sec_cm 5.740s 350.223us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.630s 38.046us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.930s 1274.706us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 114.710s 22506.302us 50 50 100.00

Error Messages

   Test seed line log context