Simulation Results: hmac

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.97 %
  • code
  • 99.34 %
  • assert
  • 97.61 %
  • func
  • 99.95 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.91 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.930s 608.431us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.340s 46.133us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.240s 39.683us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 12.980s 1226.571us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.440s 2458.486us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 211.380s 192515.436us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.240s 39.683us 20 20 100.00
hmac_csr_aliasing 6.440s 2458.486us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 73.540s 5842.792us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 110.260s 2076.700us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 280.170s 7435.516us 30 30 100.00
hmac_test_sha384_vectors 552.490s 13818.456us 75 75 100.00
hmac_test_sha512_vectors 521.760s 55558.674us 75 75 100.00
hmac_test_hmac256_vectors 16.480s 1469.104us 50 50 100.00
hmac_test_hmac384_vectors 17.380s 5499.653us 60 60 100.00
hmac_test_hmac512_vectors 18.070s 1532.216us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 35.610s 3125.197us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 942.650s 6055.939us 10 10 100.00
error 10 10 100.00
hmac_error 89.860s 3808.802us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 137.050s 50404.787us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.930s 608.431us 10 10 100.00
hmac_long_msg 73.540s 5842.792us 10 10 100.00
hmac_back_pressure 110.260s 2076.700us 25 25 100.00
hmac_datapath_stress 942.650s 6055.939us 10 10 100.00
hmac_burst_wr 35.610s 3125.197us 50 50 100.00
hmac_stress_all 2049.130s 255753.769us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.930s 608.431us 10 10 100.00
hmac_long_msg 73.540s 5842.792us 10 10 100.00
hmac_back_pressure 110.260s 2076.700us 25 25 100.00
hmac_datapath_stress 942.650s 6055.939us 10 10 100.00
hmac_wipe_secret 137.050s 50404.787us 10 10 100.00
hmac_test_sha256_vectors 280.170s 7435.516us 30 30 100.00
hmac_test_sha384_vectors 552.490s 13818.456us 75 75 100.00
hmac_test_sha512_vectors 521.760s 55558.674us 75 75 100.00
hmac_test_hmac256_vectors 16.480s 1469.104us 50 50 100.00
hmac_test_hmac384_vectors 17.380s 5499.653us 60 60 100.00
hmac_test_hmac512_vectors 18.070s 1532.216us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.930s 608.431us 10 10 100.00
hmac_long_msg 73.540s 5842.792us 10 10 100.00
hmac_back_pressure 110.260s 2076.700us 25 25 100.00
hmac_datapath_stress 942.650s 6055.939us 10 10 100.00
hmac_burst_wr 35.610s 3125.197us 50 50 100.00
hmac_error 89.860s 3808.802us 10 10 100.00
hmac_wipe_secret 137.050s 50404.787us 10 10 100.00
hmac_test_sha256_vectors 280.170s 7435.516us 30 30 100.00
hmac_test_sha384_vectors 552.490s 13818.456us 75 75 100.00
hmac_test_sha512_vectors 521.760s 55558.674us 75 75 100.00
hmac_test_hmac256_vectors 16.480s 1469.104us 50 50 100.00
hmac_test_hmac384_vectors 17.380s 5499.653us 60 60 100.00
hmac_test_hmac512_vectors 18.070s 1532.216us 75 75 100.00
hmac_stress_all 2049.130s 255753.769us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2049.130s 255753.769us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.950s 21.476us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.960s 51.271us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.680s 1085.949us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.680s 1085.949us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.340s 46.133us 5 5 100.00
hmac_csr_rw 1.240s 39.683us 20 20 100.00
hmac_csr_aliasing 6.440s 2458.486us 5 5 100.00
hmac_same_csr_outstanding 3.020s 303.654us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.340s 46.133us 5 5 100.00
hmac_csr_rw 1.240s 39.683us 20 20 100.00
hmac_csr_aliasing 6.440s 2458.486us 5 5 100.00
hmac_same_csr_outstanding 3.020s 303.654us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.580s 182.042us 5 5 100.00
hmac_tl_intg_err 4.600s 499.394us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.600s 499.394us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.930s 608.431us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.680s 278.386us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 428.660s 17663.358us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.890s 17.954us 1 1 100.00

Error Messages

   Test seed line log context