Simulation Results: keymgr

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 98.94 %
  • assert
  • 97.72 %
  • func
  • 91.13 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 98.18 %
  • toggle
  • 98.39 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.40%
V2S
99.81%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 24.860s 5797.781us 50 50 100.00
random 50 50 100.00
keymgr_random 26.400s 1636.118us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.320s 22.527us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.560s 34.453us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 12.090s 9846.946us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 10.110s 716.616us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 1.810s 65.142us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.560s 34.453us 20 20 100.00
keymgr_csr_aliasing 10.110s 716.616us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 72.540s 8003.199us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 25.080s 5980.090us 50 50 100.00
keymgr_sideload_kmac 46.310s 8853.918us 50 50 100.00
keymgr_sideload_aes 44.560s 5109.770us 50 50 100.00
keymgr_sideload_otbn 45.230s 3679.200us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 24.740s 3448.754us 50 50 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 5.030s 174.585us 50 50 100.00
kmac_error_response 48 50 96.00
keymgr_kmac_rsp_err 6.720s 505.397us 48 50 96.00
invalid_sw_input 49 50 98.00
keymgr_sw_invalid_input 38.990s 11080.254us 49 50 98.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 41.750s 3337.951us 49 50 98.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 4.630s 365.311us 49 50 98.00
stress_all 50 50 100.00
keymgr_stress_all 339.950s 15595.571us 50 50 100.00
intr_test 50 50 100.00
keymgr_intr_test 1.020s 51.771us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.370s 21.244us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.150s 625.553us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.150s 625.553us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.320s 22.527us 5 5 100.00
keymgr_csr_rw 1.560s 34.453us 20 20 100.00
keymgr_csr_aliasing 10.110s 716.616us 5 5 100.00
keymgr_same_csr_outstanding 2.510s 82.642us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.320s 22.527us 5 5 100.00
keymgr_csr_rw 1.560s 34.453us 20 20 100.00
keymgr_csr_aliasing 10.110s 716.616us 5 5 100.00
keymgr_same_csr_outstanding 2.510s 82.642us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
keymgr_tl_intg_err 7.840s 349.444us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.240s 794.090us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.240s 794.090us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.240s 794.090us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.240s 794.090us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.340s 666.924us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.840s 349.444us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.240s 794.090us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 72.540s 8003.199us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 26.400s 1636.118us 50 50 100.00
keymgr_csr_rw 1.560s 34.453us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 26.400s 1636.118us 50 50 100.00
keymgr_csr_rw 1.560s 34.453us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 26.400s 1636.118us 50 50 100.00
keymgr_csr_rw 1.560s 34.453us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 5.030s 174.585us 50 50 100.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 41.750s 3337.951us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 41.750s 3337.951us 49 50 98.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 26.400s 1636.118us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 24.580s 2190.021us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 29.750s 1348.585us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 5.030s 174.585us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 29.750s 1348.585us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 29.750s 1348.585us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 29.750s 1348.585us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.660s 3211.275us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 29.750s 1348.585us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 50 60.00
keymgr_stress_all_with_rand_reset 20.680s 4295.271us 30 50 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 75498137546528188635329611802032126520685729624630926311116018449689025319507 427
UVM_ERROR @ 218519487 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 218519487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 49093678020955466384432800745725746852654076343896086882574895596004670052811 198
UVM_ERROR @ 507587161 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 507587161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 105221037448739823073981043677017048228476556029169120951267531444446468470014 168
UVM_ERROR @ 254136187 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 254136187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 14509987885424848878404250085350392540314326162128688842713562790615857865892 338
UVM_ERROR @ 224458269 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 224458269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78497956555341308862356457211426949131396464644378635301137336798186790962063 247
UVM_ERROR @ 193344032 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 193344032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 52511791192753632034431180237556464413448597131566686668057231451911470452560 188
UVM_ERROR @ 104399895 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 104399895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 83328029492450912819255928904901634695407230837560168481210242919268217769588 436
UVM_ERROR @ 260730473 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 260730473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 42605025257152613110102310493011639669305129284045814531010755524493573079256 559
UVM_ERROR @ 3922536635 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3922536635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 110260373438891408492232295051124474279086893876215093252840845398689464477312 175
UVM_ERROR @ 252438102 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 252438102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 1789755522797777247112907740008845160162985634303849257381454864074672672227 398
UVM_ERROR @ 380342175 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 380342175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45267770931912351734310577792131128939915969831645853840470728182592282558390 1006
UVM_ERROR @ 2413667337 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2413667337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103082328204483197194171374028327351460258813755214335227070431644691523365087 145
UVM_ERROR @ 119361302 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 119361302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 64939487751497318825161952296454240052046006638464509597286606502863700584248 109
UVM_ERROR @ 769221917 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 769221917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 82437525352446675552735519001813336808137940228845423506361105273461923413479 113
UVM_ERROR @ 123412559 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123412559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87747169838180151551590501819860591268688937231761275322843982320806670483543 463
UVM_ERROR @ 294501926 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 294501926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 27350427360177177910675106059418057814326759480002877658816970974133922599045 1986
UVM_ERROR @ 4119436141 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4119436141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 98860708218518098945379759449810300684455402400394676381367110066230844412534 410
UVM_ERROR @ 405781879 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 405781879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 20438737191329978861370809596453330619990001853955807164686291713865384909595 283
UVM_ERROR @ 295593071 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 295593071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
keymgr_kmac_rsp_err 32401434159415574161070926695303396745876822316591186599093240080245913747092 526
UVM_ERROR @ 22813864 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 22813864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_hwsw_invalid_input 17853157574735208065511528974923607092894848395926110074651487536378109814037 236
UVM_ERROR @ 8361194 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 8361194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sw_invalid_input 103275110634403258603756758055947311635340741283560426439752614946766601570942 106
UVM_ERROR @ 14052671 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 14052671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sync_async_fault_cross 41538885618897485485743301408029596959207782062963643404977050775448018225171 122
UVM_ERROR @ 17443053 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 17443053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_kmac_rsp_err 66457514858082899299851148428583607504430920158536091752892263833926357443549 646
UVM_ERROR @ 210114841 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 210114841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
keymgr_stress_all_with_rand_reset 27195704081815821878848694603544509843349281784263849455129186484511301771300 710
UVM_ERROR @ 724430578 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (229958557305276066787230862443893267028691230471345014469871019516644933623724368603025995716913477012590876570979987572496991937943063983618540092397268688706585570225371562164621863959833949619298813666072628555007923599102206162699199559853070220973282857792035122319277625379807012912203210762544339065876665147760 [0x4c3ed7f8000000000000000040afcc280299bb862d5b7d74051e2634d640238e05751f4bf7071187b0ad8734865fc4df95129b112eccec560a5d61907f49701f1070b619a0197d262daa14c3784d0b2b79c39bffcb3aee4ec52151fd91a9fa072ee0ac7369802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170] vs 20337827974900980931863251856224512678629578006788948471350978632040418685825902134119996589176567765505172769467290171855055378292757239112216806415575208827117183392189946944294858489812686636355435819526883429508626614242945614394520271120305087188215270577590161799097418268346594419137776370338670977853747808858061849136800257985588476846448 [0x551c9bc600000000e15c87d900000000253d15630000000000000000000000002d5b7d74051e2634d640238e05751f4bf7071187b0ad8734865fc4df95129b112eccec560a5d61907f49701f1070b619a0197d262daa14c3784d0b2b79c39bffcb3aee4ec52151fd91a9fa072ee0ac7369802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170]) cdi_type: Attestation
HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170
RomDigest act: 0xa0197d262daa14c3784d0b2b79c39bffcb3aee4ec52151fd91a9fa072ee0ac73, exp: 0xa0197d262daa14c3784d0b2b79c39bffcb3aee4ec52151fd91a9fa072ee0ac73
HealthMeasurement act: 0x2eccec560a5d61907f49701f1070b619, exp: 0x2eccec560a5d61907f49701f1070b619
UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
keymgr_stress_all_with_rand_reset 50480444221788708162242402956673083820279522283662019534481629246267522211755 447
UVM_ERROR @ 950424458 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 950424458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---