Simulation Results: kmac

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.67 %
  • code
  • 94.33 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.20 %
  • branch
  • 97.08 %
  • cond
  • 94.49 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
99.88%
V2S
99.80%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 87.910s 15938.727us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.290s 23.469us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.420s 32.937us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.260s 3434.264us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.010s 1580.975us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.800s 300.918us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.420s 32.937us 20 20 100.00
kmac_csr_aliasing 7.010s 1580.975us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.130s 17.750us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.700s 60.448us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3469.810s 246701.505us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 1305.190s 500000.000us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1921.030s 230429.127us 5 5 100.00
kmac_test_vectors_sha3_256 2090.240s 945411.652us 5 5 100.00
kmac_test_vectors_sha3_384 1524.730s 213402.078us 5 5 100.00
kmac_test_vectors_sha3_512 1071.760s 40739.780us 5 5 100.00
kmac_test_vectors_shake_128 1801.820s 79045.537us 5 5 100.00
kmac_test_vectors_shake_256 1737.350s 58627.230us 5 5 100.00
kmac_test_vectors_kmac 3.160s 35.529us 5 5 100.00
kmac_test_vectors_kmac_xof 3.770s 136.502us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 535.170s 18052.775us 50 50 100.00
app 50 50 100.00
kmac_app 368.080s 52943.001us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 325.100s 43397.034us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 340.800s 47306.217us 50 50 100.00
error 50 50 100.00
kmac_error 513.450s 78596.080us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 16.600s 1900.727us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.490s 717.811us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 50.080s 1531.897us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 40.920s 13072.129us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 73.210s 18698.131us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 61.640s 3878.607us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2739.950s 424178.632us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.100s 30.625us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.240s 25.963us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.500s 179.459us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.500s 179.459us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.290s 23.469us 5 5 100.00
kmac_csr_rw 1.420s 32.937us 20 20 100.00
kmac_csr_aliasing 7.010s 1580.975us 5 5 100.00
kmac_same_csr_outstanding 2.390s 409.843us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.290s 23.469us 5 5 100.00
kmac_csr_rw 1.420s 32.937us 20 20 100.00
kmac_csr_aliasing 7.010s 1580.975us 5 5 100.00
kmac_same_csr_outstanding 2.390s 409.843us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.390s 350.926us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.390s 350.926us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.390s 350.926us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.390s 350.926us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 3.930s 259.334us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.100s 297.529us 20 20 100.00
kmac_sec_cm 88.890s 8687.024us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.100s 297.529us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 61.640s 3878.607us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 87.910s 15938.727us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 535.170s 18052.775us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.390s 350.926us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 88.890s 8687.024us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 88.890s 8687.024us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 88.890s 8687.024us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 87.910s 15938.727us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 61.640s 3878.607us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 88.890s 8687.024us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 313.720s 12698.000us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 87.910s 15938.727us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
kmac_stress_all_with_rand_reset 292.060s 64872.761us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 78723845458635326716375276396037997065462631993849753814189026359177574983780 429
UVM_ERROR @ 141824727 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2126274361 [0x7ebc5f39] vs 953330694 [0x38d2ac06]) Regname: kmac_reg_block.prefix_2 reset value: 0x0
UVM_INFO @ 141824727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 42780850705527272275776698183412189469899651987829943794016614721972630885161 341
UVM_ERROR @ 2914506604 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2914506604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 108700496884430949377146750545718469660094520333399006931567814326338376196852 484
UVM_ERROR @ 64872761025 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 64872761025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 112300942455935640421989423682491704561176004426625199916702372806955148730550 317
UVM_ERROR @ 4298221357 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 4298221357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 65625454798621120085538617355508494522677662067200799529368204916503229981722 382
UVM_ERROR @ 4704564060 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 4704564060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_burst_write 42212240880247042298645622722290702236936073340824610341879254568524612139449 251
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---