Simulation Results: kmac

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 92.50 %
  • assert
  • 97.74 %
  • func
  • 96.26 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 74.38 %
Validation stages
V1
100.00%
V2
98.93%
V2S
99.80%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 64.740s 3851.215us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.120s 94.317us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.020s 600.153us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.140s 1444.913us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.190s 4185.903us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.090s 170.833us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.020s 600.153us 20 20 100.00
kmac_csr_aliasing 6.190s 4185.903us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.810s 37.589us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.180s 270.022us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3481.830s 126193.760us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 914.190s 28774.414us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1602.470s 62061.843us 5 5 100.00
kmac_test_vectors_sha3_256 1515.950s 96467.040us 5 5 100.00
kmac_test_vectors_sha3_384 1231.560s 67718.689us 5 5 100.00
kmac_test_vectors_sha3_512 904.580s 513595.679us 5 5 100.00
kmac_test_vectors_shake_128 2467.770s 220638.490us 5 5 100.00
kmac_test_vectors_shake_256 1905.460s 469040.268us 5 5 100.00
kmac_test_vectors_kmac 3.220s 115.727us 5 5 100.00
kmac_test_vectors_kmac_xof 3.170s 941.850us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 417.690s 14339.097us 50 50 100.00
app 50 50 100.00
kmac_app 314.340s 64567.893us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 287.830s 18476.603us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 460.620s 157747.150us 50 50 100.00
error 50 50 100.00
kmac_error 384.620s 28150.400us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 19.190s 23957.614us 50 50 100.00
sideload_invalid 41 50 82.00
kmac_sideload_invalid 137.060s 10035.491us 41 50 82.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 41.680s 1623.796us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 39.210s 2027.802us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 70.590s 45412.556us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 33.480s 730.051us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2496.940s 429097.360us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.860s 24.390us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.200s 25.200us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 2.720s 763.164us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 2.720s 763.164us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.120s 94.317us 5 5 100.00
kmac_csr_rw 1.020s 600.153us 20 20 100.00
kmac_csr_aliasing 6.190s 4185.903us 5 5 100.00
kmac_same_csr_outstanding 2.170s 448.914us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.120s 94.317us 5 5 100.00
kmac_csr_rw 1.020s 600.153us 20 20 100.00
kmac_csr_aliasing 6.190s 4185.903us 5 5 100.00
kmac_same_csr_outstanding 2.170s 448.914us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.760s 183.900us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.760s 183.900us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.760s 183.900us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.760s 183.900us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 3.570s 1805.695us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.610s 246.246us 20 20 100.00
kmac_sec_cm 67.510s 45292.157us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.610s 246.246us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 33.480s 730.051us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 64.740s 3851.215us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 417.690s 14339.097us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.760s 183.900us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 67.510s 45292.157us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 67.510s 45292.157us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 67.510s 45292.157us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 64.740s 3851.215us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 33.480s 730.051us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 67.510s 45292.157us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 189.910s 10833.764us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 64.740s 3851.215us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 285.980s 11081.151us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 51943277667148881777444592801851712518646629780120290965234912284769111143028 295
UVM_ERROR @ 56709318 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1884626860 [0x70551fac] vs 0 [0x0]) Regname: kmac_reg_block.prefix_9.prefix_0 reset value: 0x0
UVM_INFO @ 56709318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 8218481793319683386029956081633994028371091111283144251250263651677493385676 124
UVM_ERROR @ 1682253541 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1682253541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 3924864751549859474766022280387467576083087567881639472402448700827779711988 332
UVM_ERROR @ 3926693268 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3926693268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 102616165041996988594834654107989925037245487924228750304080810318379837125204 84
UVM_FATAL @ 10200268062 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1bd91000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10200268062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 93273378223565938968999482639806323873984163241805925759379923049275541168748 85
UVM_FATAL @ 10059769610 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4d009000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10059769610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16)
kmac_sideload_invalid 57056145154167539080510974266862243355752687833065396865115621902416702679734 91
UVM_FATAL @ 10259052342 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb86f3000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10259052342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 79658885439898398927131467028558836692651064333391188557854644120555653007238 76
UVM_FATAL @ 10040983485 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc658b000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10040983485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 60930309465801791127962164185082367332845577929351449142027726803328298080863 79
UVM_FATAL @ 10035491234 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1bb09000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10035491234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 15524537493399205462674739483393697401954007243834770415967232163897137868710 85
UVM_FATAL @ 10071286239 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x360f3000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10071286239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
kmac_sideload_invalid 108211309986377489622262906146067412085463269364430826848570763787213652672906 90
UVM_FATAL @ 10082902061 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7e166000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10082902061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 95446339495929456788921974963782261809433787592996211117874984735333308413464 82
UVM_FATAL @ 10295738934 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3d862000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10295738934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 79881383199196270814672586857811714296194711894818532149980069568502040267578 92
UVM_FATAL @ 11195461654 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5f53e000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 11195461654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---