Simulation Results: mbx

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.72 %
  • code
  • 91.63 %
  • assert
  • 97.01 %
  • func
  • 86.52 %
  • block
  • 96.75 %
  • line
  • 96.71 %
  • branch
  • 92.07 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
99.60%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 2 2 100.00
mbx_smoke 78.000s 20359.365us 2 2 100.00
csr_hw_reset 5 5 100.00
mbx_csr_hw_reset 2.000s 50.378us 5 5 100.00
csr_rw 20 20 100.00
mbx_csr_rw 2.000s 23.121us 20 20 100.00
csr_bit_bash 5 5 100.00
mbx_csr_bit_bash 5.000s 856.325us 5 5 100.00
csr_aliasing 5 5 100.00
mbx_csr_aliasing 2.000s 37.862us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
mbx_csr_mem_rw_with_rand_reset 3.000s 61.175us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
mbx_csr_rw 2.000s 23.121us 20 20 100.00
mbx_csr_aliasing 2.000s 37.862us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 2 2 100.00
mbx_stress 145.000s 38159.746us 2 2 100.00
mbx_max_activity 1 2 50.00
mbx_stress_zero_delays 55.000s 4554.495us 1 2 50.00
mbx_imbx_oob 2 2 100.00
mbx_imbx_oob 45.000s 10135.523us 2 2 100.00
mbx_doe_intr_msg 5 5 100.00
mbx_doe_intr_msg 24.000s 551.341us 5 5 100.00
alert_test 50 50 100.00
mbx_alert_test 2.000s 28.369us 50 50 100.00
intr_test 50 50 100.00
mbx_intr_test 3.000s 128.237us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
mbx_tl_errors 5.000s 744.105us 20 20 100.00
tl_d_illegal_access 20 20 100.00
mbx_tl_errors 5.000s 744.105us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
mbx_csr_hw_reset 2.000s 50.378us 5 5 100.00
mbx_csr_rw 2.000s 23.121us 20 20 100.00
mbx_csr_aliasing 2.000s 37.862us 5 5 100.00
mbx_same_csr_outstanding 3.000s 126.179us 20 20 100.00
tl_d_partial_access 50 50 100.00
mbx_csr_hw_reset 2.000s 50.378us 5 5 100.00
mbx_csr_rw 2.000s 23.121us 20 20 100.00
mbx_csr_aliasing 2.000s 37.862us 5 5 100.00
mbx_same_csr_outstanding 3.000s 126.179us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
mbx_sec_cm 2.000s 13.584us 5 5 100.00
mbx_tl_intg_err 3.000s 373.163us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress_zero_delays 68028769289344624577070238359956901060358570032488834546393457803956355770521 184
UVM_ERROR @ 544641001 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (1010968215 [0x3c422697] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 544641001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---