Simulation Results: otbn

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.96 %
  • code
  • 97.16 %
  • assert
  • 96.72 %
  • func
  • 100.00 %
  • block
  • 99.60 %
  • line
  • 99.70 %
  • branch
  • 95.42 %
  • toggle
  • 93.51 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.13%
V2S
95.53%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 84.810us 1 1 100.00
single_binary 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 4.000s 93.382us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 7.000s 25.673us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 7.000s 329.573us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 4.000s 113.903us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 11.000s 45.793us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 7.000s 25.673us 20 20 100.00
otbn_csr_aliasing 4.000s 113.903us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 43.000s 2372.278us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 19.000s 123.453us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 47.000s 186.606us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 106.000s 308.876us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 105.000s 463.360us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 104.000s 1016.483us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 23.000s 78.867us 58 60 96.67
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 16.000s 53.097us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 19.000s 259.893us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 36.917us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 8.000s 38.766us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 9.000s 856.435us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 9.000s 856.435us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 4.000s 93.382us 5 5 100.00
otbn_csr_rw 7.000s 25.673us 20 20 100.00
otbn_csr_aliasing 4.000s 113.903us 5 5 100.00
otbn_same_csr_outstanding 5.000s 26.890us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 4.000s 93.382us 5 5 100.00
otbn_csr_rw 7.000s 25.673us 20 20 100.00
otbn_csr_aliasing 4.000s 113.903us 5 5 100.00
otbn_same_csr_outstanding 5.000s 26.890us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 10.000s 36.438us 10 10 100.00
otbn_dmem_err 14.000s 40.555us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 12.000s 218.455us 5 5 100.00
otbn_controller_ispr_rdata_err 13.000s 32.666us 5 5 100.00
otbn_mac_bignum_acc_err 14.000s 51.605us 5 5 100.00
otbn_urnd_err 10.000s 72.328us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 6.000s 24.725us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 6.000s 19.989us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 8.000s 32.363us 10 10 100.00
tl_intg_err 22 25 88.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
otbn_tl_intg_err 24.000s 195.130us 20 20 100.00
passthru_mem_tl_intg_err 16 20 80.00
otbn_passthru_mem_tl_intg_err 34.000s 210.050us 16 20 80.00
prim_fsm_check 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
prim_count_check 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 84.810us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 14.000s 40.555us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 10.000s 36.438us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 24.000s 195.130us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 23.000s 78.867us 58 60 96.67
sec_cm_controller_fsm_local_esc 36 40 90.00
otbn_imem_err 10.000s 36.438us 10 10 100.00
otbn_dmem_err 14.000s 40.555us 15 15 100.00
otbn_zero_state_err_urnd 16.000s 53.097us 4 5 80.00
otbn_illegal_mem_acc 6.000s 24.725us 5 5 100.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_controller_fsm_sparse 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 10.000s 36.438us 10 10 100.00
otbn_dmem_err 14.000s 40.555us 15 15 100.00
otbn_zero_state_err_urnd 16.000s 53.097us 4 5 80.00
otbn_illegal_mem_acc 6.000s 24.725us 5 5 100.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_scramble_ctrl_fsm_sparse 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 23.000s 78.867us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 10.000s 36.438us 10 10 100.00
otbn_dmem_err 14.000s 40.555us 15 15 100.00
otbn_zero_state_err_urnd 16.000s 53.097us 4 5 80.00
otbn_illegal_mem_acc 6.000s 24.725us 5 5 100.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_start_stop_ctrl_fsm_sparse 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 18.000s 57.812us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 22.522us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 54.000s 118.236us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 54.000s 118.236us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 14.000s 39.512us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_stack_wr_ptr_ctr_redun 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 15.000s 87.510us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_loop_stack_ctr_redun 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 11.000s 27.233us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 11.000s 27.233us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 1 7 14.29
otbn_sec_wipe_err 818.000s 3056.023us 1 7 14.29
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 105.000s 463.360us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 13.000s 28.033us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 20.000s 45.769us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 2 5 40.00
otbn_sec_cm 461.000s 2079.474us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 501.000s 1835.803us 2 10 20.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 18547084964749973824264394306501211572463006975291278314187217761130876520677 172
UVM_ERROR @ 1043644041 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1043644041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 102254120108995081557831122835818198716809709612810689637589690772955079401290 367
UVM_ERROR @ 974249282 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 974249282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 72359544403660062955653057412128156900285963213049205516133027427180617559526 155
UVM_ERROR @ 119404899 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 119404899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 56042321934567693199953066301203584407269157423338498766707820159659156748963 306
UVM_ERROR @ 1835802602 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1835802602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 60956195750443216843721512651858463598704363166166363827576237547145191375834 201
UVM_ERROR @ 173418272 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 173418272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
otbn_zero_state_err_urnd 30789581834283632823515766897339070609086130021918924424173025211825239651811 None
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 30789581834283632823515766897339070609086130021918924424173025211825239651811 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=2736813539 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_zero_state_err_urnd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_zero_state_err_urnd.2736813539 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_zero_state_err_urnd.2736813539 -covoverwrite' seed=30789581834283632823515766897339070609086130021918924424173025211825239651811 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_zero_state_err_urnd_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 30789581834283632823515766897339070609086130021918924424173025211825239651811 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest
2025/12/27 05:28:32 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sec_wipe_err 44632753005094121482144130297895464999230055330546328880156794291533649620028 129
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 3056023212 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 3056023212 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 3056023212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 48787398498461181938983164664501116959112500984045752080066943133728191900556 112
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 58178604 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 58178604 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 58178604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 74068160996029755915706586511463422770752759552741309872713418437997676456491 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14035368 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 14035368 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14035368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 100662693573539856845484376768081436958897853208554090718818046905687087337260 109
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10124588 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 10124588 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 10124588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 79927368082899409579711983970601513884042491449890103864553884038556108411176 116
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 169361598 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 169361598 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 169361598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 3251002654478110414878816288473124695617693637344574233894540700511355349472 106
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 34014240 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 34014240 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 34014240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 105017750563581263275507686775643613028154596957145360398125878616010930879159 100
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 126277822 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 126277822 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 126277822 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 126277822 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 126277822 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 37145990164768249576659503671700303213119006214242953855699196860289610686328 107
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 230963517 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 230963517 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 230963517 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 230963517 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 230963517 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 65020201761268009812335262907160042704479646949117459589295706307184061558361 101
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 53185627 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 53185627 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 53185627 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 53185627 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 53185627 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 4090539525044732764349893109233253450762781981217577533485515581303915547259 164
UVM_FATAL @ 746671433 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 746671433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1021) virtual_sequencer [otbn_imem_err_vseq] expect alert:fatal to fire
otbn_stress_all_with_rand_reset 76481212429678453250808781390486783726066294278803999655056024302667750152105 153
UVM_ERROR @ 45508623 ps: (cip_base_vseq.sv:1021) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 45508623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 23354450983857999585245638903403511611761443595672483568662273000989820183787 218
UVM_FATAL @ 534362633 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 534362633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,300): Assertion MatchingReqURND_A has failed
otbn_escalate 103394722379002814764743042102248565140685787979538436243090891826407996268909 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,300): (time 11784156 PS) Assertion tb.MatchingReqURND_A has failed
UVM_ERROR @ 11784156 ps: (tb.sv:300) [ASSERT FAILED] MatchingReqURND_A
UVM_INFO @ 11784156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 45574443155208287701188647540317830321179845102997279282605756471852680658055 111
UVM_ERROR @ 6604234 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 6604234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 39953645692642582225694019745135964680507658731649656401638518490418126558577 98
UVM_FATAL @ 61489896 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 61489896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 58798329348635809765130917781721958847357322580419915840882145439852811919798 83
UVM_FATAL @ 3658024 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 3658024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 36763533879958813968622733775175563062859143736730792952771451811219027439493 83
UVM_FATAL @ 7226534 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 7226534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 87346913353586260423688418973828734231929343369236801012159267553905366569013 83
UVM_FATAL @ 1735084 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1735084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---