Simulation Results: rom_ctrl

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.68 %
  • code
  • 98.74 %
  • assert
  • 95.49 %
  • func
  • 98.81 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 95.39 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
81.13%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.980s 853.633us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.800s 567.885us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 5.990s 294.091us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.860s 297.269us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.090s 578.613us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.120s 145.373us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 5.990s 294.091us 20 20 100.00
rom_ctrl_csr_aliasing 5.090s 578.613us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 4.640s 557.275us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 4.960s 173.165us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.500s 221.732us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 20.470s 1650.964us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.120s 225.368us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 7.500s 2017.504us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.730s 709.807us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.730s 709.807us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.800s 567.885us 5 5 100.00
rom_ctrl_csr_rw 5.990s 294.091us 20 20 100.00
rom_ctrl_csr_aliasing 5.090s 578.613us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.720s 906.997us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.800s 567.885us 5 5 100.00
rom_ctrl_csr_rw 5.990s 294.091us 20 20 100.00
rom_ctrl_csr_aliasing 5.090s 578.613us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.720s 906.997us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.530s 3161.436us 20 20 100.00
tl_intg_err 20 25 80.00
rom_ctrl_sec_cm 280.850s 499.198us 0 5 0.00
rom_ctrl_tl_intg_err 64.190s 411.875us 20 20 100.00
prim_fsm_check 0 5 0.00
rom_ctrl_sec_cm 280.850s 499.198us 0 5 0.00
prim_count_check 0 5 0.00
rom_ctrl_sec_cm 280.850s 499.198us 0 5 0.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_compare_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 280.850s 499.198us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
rom_ctrl_sec_cm 280.850s 499.198us 0 5 0.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.980s 853.633us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.980s 853.633us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.980s 853.633us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 64.190s 411.875us 20 20 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
rom_ctrl_kmac_err_chk 7.120s 225.368us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 103.090s 16301.024us 17 20 85.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.530s 3161.436us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 280.850s 499.198us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 424.890s 18997.375us 19 20 95.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1163) [rom_ctrl_common_vseq] Check failed (vseq_done)
rom_ctrl_stress_all_with_rand_reset 103735303289120871391148451585011631156872556028711699157894730720475067635443 89
UVM_FATAL @ 2522744444 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2522744444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 144709750071296680853997025726580732968340710216806036014746851272971771430 161
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9076978ps failed at 9076978ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9115440ps failed at 9115440ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 68886175759832208109755526411548480403051343031405142397489196115717049103499 684
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 162472965ps failed at 162472965ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 162508679ps failed at 162508679ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 15353741037516611709447223264173627041307981463383715803904190999468398550868 247
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 98904049ps failed at 98904049ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 98904049ps failed at 98904049ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 28500591980002198606060012010843559350623876596327063325043688817022503862324 304
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 16901055ps failed at 16901055ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16901055ps failed at 16901055ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 110755658040396677368432470116470642527801886363952214680799774362970218832878 227
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 7819831ps failed at 7819831ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 7830248ps failed at 7830248ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 84986600592869593778054486057825522834007830129999643228200515760544700410828 91
UVM_ERROR @ 2247939725 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 2247939725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 52377516472181441954640235716573712249909550053493384219497912962769431351747 83
UVM_ERROR @ 519673676 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 519673676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 16046829583572442655400697723818951405482554987431741608181002510187595880982 77
UVM_ERROR @ 1035314818 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1035314818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---