Simulation Results: rom_ctrl

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.45%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 12.540s 1274.416us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 17.190s 210.554us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 11.430s 340.103us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 11.830s 287.347us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 11.000s 790.551us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.950s 312.898us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 11.430s 340.103us 20 20 100.00
rom_ctrl_csr_aliasing 11.000s 790.551us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 9.090s 1543.044us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 11.530s 296.213us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 9.650s 697.485us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 54.830s 2027.357us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.130s 2021.940us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 11.820s 297.399us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 17.020s 2094.524us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 17.020s 2094.524us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 17.190s 210.554us 5 5 100.00
rom_ctrl_csr_rw 11.430s 340.103us 20 20 100.00
rom_ctrl_csr_aliasing 11.000s 790.551us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.590s 1097.877us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 17.190s 210.554us 5 5 100.00
rom_ctrl_csr_rw 11.430s 340.103us 20 20 100.00
rom_ctrl_csr_aliasing 11.000s 790.551us 5 5 100.00
rom_ctrl_same_csr_outstanding 16.590s 1097.877us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.910s 6957.998us 20 20 100.00
tl_intg_err 21 25 84.00
rom_ctrl_sec_cm 529.120s 655.778us 1 5 20.00
rom_ctrl_tl_intg_err 149.840s 1386.411us 20 20 100.00
prim_fsm_check 1 5 20.00
rom_ctrl_sec_cm 529.120s 655.778us 1 5 20.00
prim_count_check 1 5 20.00
rom_ctrl_sec_cm 529.120s 655.778us 1 5 20.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_compare_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 529.120s 655.778us 1 5 20.00
sec_cm_fsm_sparse 1 5 20.00
rom_ctrl_sec_cm 529.120s 655.778us 1 5 20.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 12.540s 1274.416us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 12.540s 1274.416us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 12.540s 1274.416us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 149.840s 1386.411us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
rom_ctrl_kmac_err_chk 16.130s 2021.940us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 292.810s 8953.118us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.910s 6957.998us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 529.120s 655.778us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 401.770s 46965.348us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 2281136234720595908361274942780936713441974366573701295628943033123042234752 174
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16341035ps failed at 16341035ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16351239ps failed at 16351239ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 85194449669826643600421017884569730274750079330412583309190259956834472594730 106
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 1094604ps failed at 1094604ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 1104808ps failed at 1104808ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 14623066656477922118619093348210835491819463960312511951323985771250152357320 235
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 13479219ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 13479219ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 13479219ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 16063250555531080966660091228827786578555864883611198660602096938138213682237 236
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 47740535ps failed at 47740535ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 47740535ps failed at 47740535ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'