Simulation Results: rstmgr

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.59 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.670s 68.590us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.110s 64.046us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.040s 36.316us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 3.620s 144.073us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.200s 49.640us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.840s 98.595us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.040s 36.316us 20 20 100.00
rstmgr_csr_aliasing 1.200s 49.640us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.720s 131.263us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.400s 47.418us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.430s 103.026us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 6.090s 811.048us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 6.090s 811.048us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 6.090s 811.048us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 6.090s 811.048us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 37.070s 5574.612us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.820s 142.459us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.150s 47.705us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.150s 47.705us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.110s 64.046us 5 5 100.00
rstmgr_csr_rw 1.040s 36.316us 20 20 100.00
rstmgr_csr_aliasing 1.200s 49.640us 5 5 100.00
rstmgr_same_csr_outstanding 1.200s 75.273us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.110s 64.046us 5 5 100.00
rstmgr_csr_rw 1.040s 36.316us 20 20 100.00
rstmgr_csr_aliasing 1.200s 49.640us 5 5 100.00
rstmgr_same_csr_outstanding 1.200s 75.273us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_tl_intg_err 4.630s 741.383us 20 20 100.00
rstmgr_sec_cm 21.660s 4239.890us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 21.660s 4239.890us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 21.660s 4239.890us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 4.630s 741.383us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.610s 65.896us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 4.050s 464.175us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 2.310s 292.575us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 21.660s 4239.890us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.040s 36.316us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.040s 36.316us 20 20 100.00

Error Messages

   Test seed line log context