Simulation Results: spi_host

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.65%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 97.000s 26892.624us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 85.072us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 54.112us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 160.324us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 26.934us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 3.000s 117.402us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 54.112us 20 20 100.00
spi_host_csr_aliasing 2.000s 26.934us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 67.136us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 53.490us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 3.000s 133.014us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 35.000s 894.589us 50 50 100.00
spi_host_error_cmd 2.000s 45.085us 50 50 100.00
spi_host_event 682.000s 89735.655us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 11.000s 878.339us 50 50 100.00
speed 50 50 100.00
spi_host_speed 11.000s 878.339us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 11.000s 878.339us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 137.000s 7088.759us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 110.076us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 11.000s 878.339us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 11.000s 878.339us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 97.000s 26892.624us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 97.000s 26892.624us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 114.000s 14348.365us 50 50 100.00
spien 49 50 98.00
spi_host_spien 149.000s 9159.394us 49 50 98.00
stall 47 50 94.00
spi_host_status_stall 1942.000s 1000000.000us 47 50 94.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 39.000s 4293.852us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 35.000s 894.589us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 90.044us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 17.442us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 778.118us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 778.118us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 85.072us 5 5 100.00
spi_host_csr_rw 2.000s 54.112us 20 20 100.00
spi_host_csr_aliasing 2.000s 26.934us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 271.791us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 85.072us 5 5 100.00
spi_host_csr_rw 2.000s 54.112us 20 20 100.00
spi_host_csr_aliasing 2.000s 26.934us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 271.791us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 64.951us 5 5 100.00
spi_host_tl_intg_err 2.000s 92.753us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 92.753us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 552.000s 63255.674us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: *
spi_host_status_stall 111650921592940749921616476967593428947443101862393459817774947599679142854399 738
UVM_ERROR @ 182816068 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
UVM_INFO @ 182816068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_status_stall 105813257806935930973603094009071950214857051852589606417260965674811516191400 2953
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 26023926743655172469563953721984202911076655229730470713250380647841342755025 2050
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_spien 77692886033818099836880551649602032774872831630992860623920551200788070769345 408
UVM_FATAL @ 10646532279 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xf4a3b194, Comparison=CompareOpEq, exp_data=0x0, call_count=68
UVM_INFO @ 10646532279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---