Simulation Results: sram_ctrl

 
26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.49%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 99.520s 1959.392us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.070s 45.214us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.090s 15.498us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.090s 478.400us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.130s 18.240us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.330s 350.720us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.090s 15.498us 20 20 100.00
sram_ctrl_csr_aliasing 1.130s 18.240us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 355.620s 197333.306us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 196.050s 98120.079us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1438.820s 115631.779us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 356.660s 11192.579us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2804.570s 1763434.176us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1838.990s 219754.351us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 117.960s 64983.403us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1381.760s 27694.167us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 111.080s 10664.826us 50 50 100.00
sram_ctrl_partial_access_b2b 630.190s 54928.996us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 88.700s 3186.431us 50 50 100.00
sram_ctrl_throughput_w_partial_write 91.950s 2005.607us 50 50 100.00
sram_ctrl_throughput_w_readback 102.240s 4790.326us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1364.970s 49447.349us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 7.610s 6675.787us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 8290.950s 1188688.952us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.080s 13.597us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.890s 38.905us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.890s 38.905us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 45.214us 5 5 100.00
sram_ctrl_csr_rw 1.090s 15.498us 20 20 100.00
sram_ctrl_csr_aliasing 1.130s 18.240us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.110s 31.503us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 45.214us 5 5 100.00
sram_ctrl_csr_rw 1.090s 15.498us 20 20 100.00
sram_ctrl_csr_aliasing 1.130s 18.240us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.110s 31.503us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 80.780s 28194.134us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.170s 11.268us 0 5 0.00
sram_ctrl_tl_intg_err 3.320s 206.765us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.170s 11.268us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.320s 206.765us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1364.970s 49447.349us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1364.970s 49447.349us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.090s 15.498us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1381.760s 27694.167us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1381.760s 27694.167us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1381.760s 27694.167us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 117.960s 64983.403us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 48 50 96.00
sram_ctrl_mubi_enc_err 11.210s 13365.248us 48 50 96.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 80.780s 28194.134us 20 20 100.00
sec_cm_mem_readback 39 50 78.00
sram_ctrl_readback_err 12.750s 13200.106us 39 50 78.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 99.520s 1959.392us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 99.520s 1959.392us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1381.760s 27694.167us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.170s 11.268us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 117.960s 64983.403us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.170s 11.268us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.170s 11.268us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 99.520s 1959.392us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.170s 11.268us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 191.580s 1864.145us 50 50 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 100795469455579886011998855042329672085652595765704980523936227469741780620310 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 11267994 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 11267994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 65506222657777903887473006098538442550099429946281502599444803239528317853481 96
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 4533244 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 4533244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 98669437718328147953775769209071942001346045821977583979797354832885603040246 98
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 27245887 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 27245887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 87259829723573958526317568638181623279816125925567562205533764454600754042594 96
UVM_ERROR @ 10994191 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 10994191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 111113954377680222888106260366536135306813750472019684871211037537992649927166 99
UVM_ERROR @ 9099105 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 9099105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 50676908630250135164413236499002256967782643619175161892828567898800798626111 95
UVM_ERROR @ 4696755040 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3e) != exp (0x73)
UVM_INFO @ 4696755040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 5102919217609846795265308459819578336266174944578142961612721510017570547821 95
UVM_ERROR @ 4695387120 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x51) != exp (0xf)
UVM_INFO @ 4695387120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 11145664336854637620137758057329326113497931557970197449819807589756795650525 95
UVM_ERROR @ 2636939721 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x9) != exp (0x50)
UVM_INFO @ 2636939721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 12237659881061769356815491987857006619952626018972068100233964028804115536891 95
UVM_ERROR @ 1341767169 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7) != exp (0x5b)
UVM_INFO @ 1341767169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 20849585858219836495390202213036063674011042280270396491539649608542622268380 95
UVM_ERROR @ 2067204149 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x64) != exp (0x52)
UVM_INFO @ 2067204149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 49014769891110191786515307479100549140176399261931718098716449215191640828070 95
UVM_ERROR @ 2738322548 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x13) != exp (0x57)
UVM_INFO @ 2738322548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 89694623992502615279231376695394064072184004278798892040208629508209913949131 95
UVM_ERROR @ 2738175079 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x19) != exp (0x14)
UVM_INFO @ 2738175079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 44103335465197736359469851106887295524922012431259995733755034554852810214357 95
UVM_ERROR @ 1370867836 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x27) != exp (0x3d)
UVM_INFO @ 1370867836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 28972016562376382191511746459519544984940341373456950779824632879470763010027 95
UVM_ERROR @ 670286880 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7e) != exp (0x6)
UVM_INFO @ 670286880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 26235299788735594403831999871877674294546477134512046817079389846234492995106 95
UVM_ERROR @ 1345506737 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x73) != exp (0x2a)
UVM_INFO @ 1345506737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 72184691374523623528415116034716204014664156978246636343817968958751905799405 95
UVM_ERROR @ 753857134 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1c) != exp (0x4d)
UVM_INFO @ 753857134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 99939825999709163304985453219800579930138622027460074842340051783478799709423 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3034383777 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3034383777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 82634614327152663877930357081343334241751121341061782779681511082164146920888 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 821900157 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 821900157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---