sram_ctrl Simulation Results

Simulation Results: sram_ctrl

26/12/2025 17:03:56 sha: 3043786 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.75 %

code
96.12 %

assert
95.79 %

func
98.33 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.89%
V2S		93.21%
V3		100.00%

230/230 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	103.680s	3737.390us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	0.970s	50.979us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.060s	15.070us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	2.210s	126.795us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	0.970s	12.259us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.740s	94.576us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.060s	15.070us	20	20	100.00
	sram_ctrl_csr_aliasing	0.970s	12.259us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	13.920s	661.530us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.700s	204.304us	50	50	100.00

889/890 passed

99.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1562.730s	25239.769us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	409.790s	4201.582us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	92.410s	4498.477us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1181.560s	17496.499us	50	50	100.00
lc_escalation				49	50	98.00
	sram_ctrl_lc_escalation	11.320s	1812.849us	49	50	98.00
executable				50	50	100.00
	sram_ctrl_executable	1177.640s	43018.549us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	92.170s	650.398us	50	50	100.00
	sram_ctrl_partial_access_b2b	514.910s	43447.575us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	101.570s	1859.634us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	96.310s	646.427us	50	50	100.00
	sram_ctrl_throughput_w_readback	99.210s	1145.116us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1186.700s	42528.919us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.200s	53.455us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4277.210s	66212.399us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.070s	12.531us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.810s	158.998us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.810s	158.998us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.970s	50.979us	5	5	100.00
	sram_ctrl_csr_rw	1.060s	15.070us	20	20	100.00
	sram_ctrl_csr_aliasing	0.970s	12.259us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.120s	36.164us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.970s	50.979us	5	5	100.00
	sram_ctrl_csr_rw	1.060s	15.070us	20	20	100.00
	sram_ctrl_csr_aliasing	0.970s	12.259us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.120s	36.164us	20	20	100.00

V2S

727/780 passed

93.21 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.300s	404.516us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	1.200s	18.152us	0	5	0.00
	sram_ctrl_tl_intg_err	2.920s	860.151us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.200s	18.152us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	2.920s	860.151us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1186.700s	42528.919us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1186.700s	42528.919us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.060s	15.070us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1177.640s	43018.549us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1177.640s	43018.549us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1177.640s	43018.549us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				49	50	98.00
	sram_ctrl_lc_escalation	11.320s	1812.849us	49	50	98.00
sec_cm_prim_ram_ctrl_mubi				43	50	86.00
	sram_ctrl_mubi_enc_err	1.620s	51.152us	43	50	86.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.300s	404.516us	20	20	100.00
sec_cm_mem_readback				36	50	72.00
	sram_ctrl_readback_err	1.590s	49.653us	36	50	72.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	103.680s	3737.390us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	103.680s	3737.390us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1177.640s	43018.549us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.200s	18.152us	0	5	0.00
sec_cm_key_global_esc				49	50	98.00
	sram_ctrl_lc_escalation	11.320s	1812.849us	49	50	98.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.200s	18.152us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.200s	18.152us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	103.680s	3737.390us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.200s	18.152us	0	5	0.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	sram_ctrl_stress_all_with_rand_reset	589.330s	2430.767us	50	50	100.00

Error Messages

	Test	seed	line	log context
Offending '(depth_o <= *'(Depth))'
	sram_ctrl_sec_cm	90074879503646404525035961802108827760773627240538433577514388300206743107410	98	Offending '(depth_o <= 2'(Depth))' UVM_ERROR @ 9027925 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth UVM_INFO @ 9027925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	67609677949160961969743519737780572094427209583227603880854680078106567088828	97	UVM_ERROR @ 2836854 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 2836854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	86248293208227389244650033717352261951540834113887829436271769129094456440457	99	UVM_ERROR @ 18152155 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 18152155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	16187268332402480611291518682048400261425621942750306006049811870609334954538	96	UVM_ERROR @ 1762172 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 1762172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	31858018088651634729602924217696664611841073664547773487622587362644240893660	95	UVM_ERROR @ 45794086 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x44) != exp (0x32) UVM_INFO @ 45794086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	44196543355090090489576354652737030746639937514401731306615003929507571394694	95	UVM_ERROR @ 28760010 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2c) != exp (0x76) UVM_INFO @ 28760010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	37892528968245518302864939223207728248219571022283935552953858606581060482126	95	UVM_ERROR @ 331743104 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x60) UVM_INFO @ 331743104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	51338278256028399543406616139484192904667719932107391166106721417696310166360	95	UVM_ERROR @ 157968793 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x4c) UVM_INFO @ 157968793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	78210696788358352002161852722060415105503048846422097890016272095290684559553	95	UVM_ERROR @ 93136396 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x56) != exp (0x45) UVM_INFO @ 93136396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	40261193319562359611406619030494373625311302433305294680725526919690716276559	95	UVM_ERROR @ 39260122 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x28) != exp (0x63) UVM_INFO @ 39260122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	30422845427524169937954915717272295991628237198994211926583535082295525519999	95	UVM_ERROR @ 103692235 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x72) UVM_INFO @ 103692235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	56064170037127900509472424379570467208602370485757696134109920160029753708976	95	UVM_ERROR @ 48955158 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x41) != exp (0x5c) UVM_INFO @ 48955158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	28870637229193961875713799535784518703486976858705863521867594384868692656518	95	UVM_ERROR @ 26434027 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x73) != exp (0x62) UVM_INFO @ 26434027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	56755624197984176787390640778959890601449476958817045799593056723826963710447	95	UVM_ERROR @ 28137790 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x65) != exp (0x25) UVM_INFO @ 28137790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	43548257485534242609028737109068236352331325964817044308492334693042646588431	95	UVM_ERROR @ 23310914 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xe) != exp (0x25) UVM_INFO @ 23310914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	28165379299056082495852955739053584829220328781984268572321996646853391114216	95	UVM_ERROR @ 96203631 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1e) != exp (0x22) UVM_INFO @ 96203631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	68001335494675705899698382994968751158838310481449341815788160065604816037284	95	UVM_ERROR @ 51792986 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x58) UVM_INFO @ 51792986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	8004379867272720848863380839438566594611925259450633602413633479872838057361	95	UVM_ERROR @ 23364257 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x38) != exp (0x3c) UVM_INFO @ 23364257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
	sram_ctrl_sec_cm	16295329783922728678021385815789898533359765753898180326108006877833501596726	98	Offending '(!$isunknown(rdata_o))' UVM_ERROR @ 12921449 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 12921449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	40155144029744107062405824374676129409903299288192032935265197083536164180468	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 341062337 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 341062337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	14922811384225312903165937199025374928986673388669860713375592829456338533336	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 80719014 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 80719014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	114894198272190196365313787414166315117595325587745777330071818750407290484579	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 91262424 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 91262424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	56125594337749925015540931564075968442096304135396706772221979811085316803157	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 96964739 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 96964739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	53066060792145916405220330444809849660966256125783565915266997994252898387591	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 41298583 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 41298583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	50185311821489324563392730552674107214473896693252699221673799892179090979255	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 113345811 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 113345811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	30734942229474215475454093145522250814956632920978542800550961509829376186956	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 48803070 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 48803070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [] vs []) addr read out mismatch
	sram_ctrl_lc_escalation	113548127808098937079973116103684519597285428852192288956013214355742954901317	93	UVM_ERROR @ 174942571 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0x3f [111111] vs 0xcb [11001011]) addr 0x5ca14974 read out mismatch UVM_INFO @ 174942571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---