ac_range_check Simulation Results

Simulation Results: ac_range_check

02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.28 %

code
93.54 %

assert
97.63 %

func
58.67 %

block
99.21 %

line
99.94 %

branch
98.35 %

toggle
82.34 %

Validation stages

V1		97.50%
V2		97.11%
V2S		100.00%
V3		100.00%
unmapped		100.00%

117/120 passed

97.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_smoke				20	20	100.00
	ac_range_check_smoke	66.000s	12957.901us	20	20	100.00
ac_range_check_smoke_racl				17	20	85.00
	ac_range_check_smoke_racl	81.000s	4788.650us	17	20	85.00
csr_hw_reset				5	5	100.00
	ac_range_check_csr_hw_reset	3.000s	171.323us	5	5	100.00
csr_rw				20	20	100.00
	ac_range_check_csr_rw	4.000s	180.299us	20	20	100.00
csr_bit_bash				5	5	100.00
	ac_range_check_csr_bit_bash	43.000s	6856.936us	5	5	100.00
csr_aliasing				5	5	100.00
	ac_range_check_csr_aliasing	33.000s	2527.423us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	ac_range_check_csr_mem_rw_with_rand_reset	4.000s	49.072us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	ac_range_check_csr_rw	4.000s	180.299us	20	20	100.00
	ac_range_check_csr_aliasing	33.000s	2527.423us	5	5	100.00

302/311 passed

97.11 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_lock_range				20	20	100.00
	ac_range_check_lock_range	5.000s	251.833us	20	20	100.00
ac_range_bypass_enable				1	1	100.00
	ac_range_check_bypass	50.000s	1475.980us	1	1	100.00
stress_all				41	50	82.00
	ac_range_check_stress_all	322.000s	9852.251us	41	50	82.00
alert_test				50	50	100.00
	ac_range_check_alert_test	3.000s	15.409us	50	50	100.00
intr_test				50	50	100.00
	ac_range_check_intr_test	2.000s	15.771us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	ac_range_check_tl_errors	7.000s	704.275us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	ac_range_check_tl_errors	7.000s	704.275us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	171.323us	5	5	100.00
	ac_range_check_csr_rw	4.000s	180.299us	20	20	100.00
	ac_range_check_csr_aliasing	33.000s	2527.423us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	1989.467us	20	20	100.00
tl_d_partial_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	171.323us	5	5	100.00
	ac_range_check_csr_rw	4.000s	180.299us	20	20	100.00
	ac_range_check_csr_aliasing	33.000s	2527.423us	5	5	100.00
	ac_range_check_same_csr_outstanding	8.000s	1989.467us	20	20	100.00

V2S

125/125 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	ac_range_check_shadow_reg_errors	24.000s	3626.051us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	ac_range_check_shadow_reg_errors	24.000s	3626.051us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	ac_range_check_shadow_reg_errors	24.000s	3626.051us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	ac_range_check_shadow_reg_errors	24.000s	3626.051us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	ac_range_check_shadow_reg_errors_with_csr_rw	164.000s	21217.008us	20	20	100.00
tl_intg_err				25	25	100.00
	ac_range_check_tl_intg_err	17.000s	1484.112us	20	20	100.00
	ac_range_check_sec_cm	2.000s	25.387us	5	5	100.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	ac_range_check_stress_all_with_rand_reset	399.000s	5372.952us	50	50	100.00

unmapped

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				20	20	100.00
	ac_range_check_smoke_high_threshold	57.000s	5737.025us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: ac_range_check_reg_block.intr_state
	ac_range_check_stress_all	61742057688163720510036524271387461593560495316051597274174511271711666724222	18021	UVM_ERROR @ 5531972988 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5531972988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	34459452520100303546633430020437952987101332675203967095535430210975191251914	4083	UVM_ERROR @ 8602847438 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 8602847438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	57218442276937943915908544363588815868047261298904007743459965126573864270706	4039	UVM_ERROR @ 1181389346 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 1181389346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	44586939088538308276586639924452632627530334034291864398284562000673080124129	9047	UVM_ERROR @ 5515310763 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5515310763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	99454118116438271501221882108214306148179911200290986189392356348325288344007	4283	UVM_ERROR @ 1674033961 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 1674033961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	112691551388842091899441528954409569287773800109649160550164874320383097150359	22266	UVM_ERROR @ 94321378822 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 94321378822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	89438405195879260289249728441656475725241214367133315950560908582982544531524	9283	UVM_ERROR @ 7655551168 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 7655551168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	21037066531940142889105130250403070841099015702174251905593497112934730959896	13224	UVM_ERROR @ 5406989286 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5406989286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	33527230659343742504925426892581362566876569699367342878189412285572649963036	8955	UVM_ERROR @ 3170668293 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 3170668293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	113080926868977945787392179967594337235137767696605917862045389060793017218425	8603	UVM_ERROR @ 1142130449 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 1142130449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	100541216120141008575312358938997526163426834088193703359287558218441479613665	23152	UVM_ERROR @ 5025045132 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 5025045132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	3927711781338978161596530942717036902442788430018742032478024231099018535422	22314	UVM_ERROR @ 18066993855 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state UVM_INFO @ 18066993855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---