Simulation Results: aes

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.65 %
  • code
  • 92.95 %
  • assert
  • 98.40 %
  • func
  • 98.60 %
  • block
  • 96.22 %
  • line
  • 97.40 %
  • branch
  • 90.72 %
  • toggle
  • 98.08 %
  • FSM
  • 85.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.34%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 105.358us 1 1 100.00
smoke 50 50 100.00
aes_smoke 12.000s 597.726us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 123.019us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 71.083us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 7.000s 1213.905us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 84.717us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 57.762us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 71.083us 20 20 100.00
aes_csr_aliasing 3.000s 84.717us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 12.000s 597.726us 50 50 100.00
aes_config_error 12.000s 484.850us 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
key_length 150 150 100.00
aes_smoke 12.000s 597.726us 50 50 100.00
aes_config_error 12.000s 484.850us 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
back2back 100 100 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
aes_b2b 35.000s 537.561us 50 50 100.00
backpressure 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 12.000s 597.726us 50 50 100.00
aes_config_error 12.000s 484.850us 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
aes_alert_reset 7.000s 455.358us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 5.000s 179.240us 50 50 100.00
aes_config_error 12.000s 484.850us 50 50 100.00
aes_alert_reset 7.000s 455.358us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 14.000s 523.853us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 2103.903us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 7.000s 455.358us 50 50 100.00
stress 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
sideload 100 100 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
aes_sideload 19.000s 900.813us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 13.000s 924.540us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 856.000s 40014.779us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 95.113us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 475.092us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 475.092us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 123.019us 5 5 100.00
aes_csr_rw 3.000s 71.083us 20 20 100.00
aes_csr_aliasing 3.000s 84.717us 5 5 100.00
aes_same_csr_outstanding 3.000s 218.935us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 123.019us 5 5 100.00
aes_csr_rw 3.000s 71.083us 20 20 100.00
aes_csr_aliasing 3.000s 84.717us 5 5 100.00
aes_same_csr_outstanding 3.000s 218.935us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 10.000s 400.712us 50 50 100.00
fault_inject 677 700 96.71
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 160.014us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 160.014us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 160.014us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 160.014us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 242.613us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 6.000s 1216.781us 5 5 100.00
aes_tl_intg_err 3.000s 875.438us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 3.000s 875.438us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 7.000s 455.358us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 160.014us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 160.014us 20 20 100.00
sec_cm_main_config_sparse 220 220 100.00
aes_smoke 12.000s 597.726us 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
aes_alert_reset 7.000s 455.358us 50 50 100.00
aes_core_fi 19.000s 6080.659us 70 70 100.00
sec_cm_gcm_config_sparse 100 100 100.00
aes_config_error 12.000s 484.850us 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 160.014us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 70.625us 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
aes_sideload 19.000s 900.813us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 70.625us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 70.625us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 70.625us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 70.625us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 70.625us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 41.000s 3059.473us 50 50 100.00
sec_cm_main_fsm_sparse 49 50 98.00
aes_fi 18.000s 990.931us 49 50 98.00
sec_cm_main_fsm_redun 727 750 96.93
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
aes_ctr_fi 5.000s 831.370us 50 50 100.00
sec_cm_cipher_fsm_sparse 49 50 98.00
aes_fi 18.000s 990.931us 49 50 98.00
sec_cm_cipher_fsm_redun 677 700 96.71
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
sec_cm_cipher_ctr_redun 343 350 98.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
sec_cm_ctr_fsm_sparse 49 50 98.00
aes_fi 18.000s 990.931us 49 50 98.00
sec_cm_ctr_fsm_redun 384 400 96.00
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_ctr_fi 5.000s 831.370us 50 50 100.00
sec_cm_ctrl_sparse 727 750 96.93
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
aes_ctr_fi 5.000s 831.370us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 7.000s 455.358us 50 50 100.00
sec_cm_main_fsm_local_esc 727 750 96.93
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
aes_ctr_fi 5.000s 831.370us 50 50 100.00
sec_cm_cipher_fsm_local_esc 727 750 96.93
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
aes_ctr_fi 5.000s 831.370us 50 50 100.00
sec_cm_ctr_fsm_local_esc 384 400 96.00
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_ctr_fi 5.000s 831.370us 50 50 100.00
sec_cm_data_reg_local_esc 677 700 96.71
aes_fi 18.000s 990.931us 49 50 98.00
aes_control_fi 50.000s 10008.698us 285 300 95.00
aes_cipher_fi 31.000s 10008.639us 343 350 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 49.000s 869.301us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 25560499943567407946387428204707246966248361077791855463583949756451147944191 148
UVM_FATAL @ 10018667427 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10018667427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 37015063346156627277424473806042540338449308418382996882651196216422213583912 142
UVM_FATAL @ 10006756602 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006756602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 105558693059671688808635355027007914393413851435448602806085573546447239606456 145
UVM_FATAL @ 10015546422 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015546422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 78489735338374343984570708395072581875608704166013942794357303622786123418970 143
UVM_FATAL @ 10046225764 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10046225764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 76069814331299720849136619962016060069644989710282270071626019079955744669507 143
UVM_FATAL @ 10008638640 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008638640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15324575330997460076781172304872175300606326507360889933049462965502957467986 146
UVM_FATAL @ 10013458606 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013458606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 3261661938866886654788637133656792628306567612153239998298603999007627480028 216
UVM_FATAL @ 239716897 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 239716897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 4256355399358333997332886089850519590696182344683049772685838595625622721887 904
UVM_FATAL @ 591552673 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 591552673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 44345378110339459732379239466358371126476428270025356234048242232614391440143 775
UVM_FATAL @ 4749726726 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 4749726726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 5819802688286300863753534355770272591094001082157284357920821767477243925058 827
UVM_FATAL @ 3480574153 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 3480574153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 55129705749975671231950738883720769177195647957638157065064047449203834369509 273
UVM_FATAL @ 625759432 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 625759432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 9898849136379343813294949562475964059464208111314353116571464259350561306938 294
UVM_ERROR @ 358091492 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 358091492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 81400918470267858969027033430785231017343728640229521008154013017277201494903 443
UVM_ERROR @ 1842102103 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1842102103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 85189137779231236326665015112365906895516492685510756011974487290446829985849 662
UVM_ERROR @ 995333023 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 995333023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 64338430795273063686847807767850089989946048971358274500613423090913796942843 1315
UVM_ERROR @ 869301136 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 869301136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 87950150573248069267111481562205583029940527619093306527237342512100061773002 266
UVM_ERROR @ 3004579896 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3004579896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
aes_cipher_fi 61526761288593239453393861685312209727687344598229683955590124032526851050083 None
Job timed out after 1 minutes
aes_control_fi 4886609627044500790472722930460400676567448191910281073273371487195408720077 None
Job timed out after 1 minutes
aes_control_fi 73129735319766537456149630257689677672214490104733030483774340214610955449697 None
Job timed out after 1 minutes
aes_control_fi 10637608821146290149046528738786580372923061815777567399903405126939436142594 None
Job timed out after 1 minutes
aes_control_fi 25558378807353509502722745425994783760516403286286912634539094462753721643560 None
Job timed out after 1 minutes
aes_control_fi 61818206443907667830151965282394680675814245176290781179653485809572369945422 None
Job timed out after 1 minutes
aes_control_fi 27604249805597389872573235192270182456559524708366997672896591273348856174815 None
Job timed out after 1 minutes
aes_control_fi 93394851435491215489054167214958638897300821280897012900209509009718016881274 None
Job timed out after 1 minutes
aes_control_fi 103664702126409135703891226430325813931085191276260337216772598729819085926056 None
Job timed out after 1 minutes
aes_control_fi 21485905458333234507542118233507900934527979959379560777972718746524009662521 None
Job timed out after 1 minutes
aes_control_fi 46830410071818930941015009678785344848967516798062725951618093815176018981477 None
Job timed out after 1 minutes
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 15120322116077302785794711997695261735308814432830758435454632157664128486035 148
UVM_FATAL @ 10015884583 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015884583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 19137473796699283771094889311167015571512250616419268801189071261955014298739 141
UVM_FATAL @ 10008697956 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008697956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 100107130382366710486739875255234356406692686692671652893772371221813796056023 137
UVM_FATAL @ 10010368416 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010368416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 89031416748924092094272798301265160714553615151164224351940485251428190662444 142
UVM_FATAL @ 10039724796 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10039724796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 87785868493187450853994501682804481324593643797519518392215449203105620614601 142
UVM_FATAL @ 10089878885 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10089878885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset
aes_fi 112473831361215222315713001565666331794047168695848709294551090324175035788857 8066
UVM_FATAL @ 181430148 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
UVM_INFO @ 181430148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---