Simulation Results: dma

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.37 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 76.95 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 19.000s 1249.272us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 18.000s 1469.370us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 30.000s 1565.307us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 19.800us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 26.918us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 14.000s 5371.904us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 8.000s 2055.270us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 47.298us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 26.918us 20 20 100.00
dma_csr_aliasing 8.000s 2055.270us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 139.000s 29865.672us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 616.000s 150663.996us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 1366.000s 196154.030us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 1366.000s 196154.030us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 616.000s 150663.996us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 954.000s 90693.070us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 1366.000s 196154.030us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 31.000s 1691.519us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 183.000s 58485.931us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 17.697us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 21.115us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 160.960us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 160.960us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 19.800us 5 5 100.00
dma_csr_rw 2.000s 26.918us 20 20 100.00
dma_csr_aliasing 8.000s 2055.270us 5 5 100.00
dma_same_csr_outstanding 4.000s 829.800us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 19.800us 5 5 100.00
dma_csr_rw 2.000s 26.918us 20 20 100.00
dma_csr_aliasing 8.000s 2055.270us 5 5 100.00
dma_same_csr_outstanding 4.000s 829.800us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 39.000s 98.805us 5 5 100.00
dma_generic_stress 954.000s 90693.070us 5 5 100.00
dma_handshake_stress 1366.000s 196154.030us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 12.000s 5200.888us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 13.899us 5 5 100.00
dma_tl_intg_err 5.000s 172.470us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 243.000s 30162.226us 25 25 100.00
dma_longer_transfer 8.000s 891.888us 5 5 100.00
dma_stress_all_with_rand_reset 4.000s 107.484us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 9131674022725425132647345693903989991220561384291889757622955388022877309998 90
UVM_ERROR @ 107483957ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107483957ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---