Simulation Results: edn

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.36 %
  • code
  • 95.81 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.02 %
  • toggle
  • 97.12 %
  • FSM
  • 92.47 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.410s 19.961us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.960s 22.221us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.030s 40.992us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.090s 175.042us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.540s 61.007us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.800s 26.614us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.030s 40.992us 20 20 100.00
edn_csr_aliasing 1.540s 61.007us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 68.650s 5251.317us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 68.650s 5251.317us 300 300 100.00
genbits 300 300 100.00
edn_genbits 68.650s 5251.317us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.570s 21.645us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.740s 54.156us 200 200 100.00
errs 100 100 100.00
edn_err 1.640s 53.547us 100 100 100.00
disable 100 100 100.00
edn_disable 1.300s 12.127us 50 50 100.00
edn_disable_auto_req_mode 1.860s 46.331us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 7.650s 503.305us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.990s 18.717us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.480s 77.336us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.710s 667.081us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.710s 667.081us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.960s 22.221us 5 5 100.00
edn_csr_rw 1.030s 40.992us 20 20 100.00
edn_csr_aliasing 1.540s 61.007us 5 5 100.00
edn_same_csr_outstanding 1.230s 277.202us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.960s 22.221us 5 5 100.00
edn_csr_rw 1.030s 40.992us 20 20 100.00
edn_csr_aliasing 1.540s 61.007us 5 5 100.00
edn_same_csr_outstanding 1.230s 277.202us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 9.950s 7687.975us 5 5 100.00
edn_tl_intg_err 4.500s 321.583us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.290s 36.953us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.740s 54.156us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.950s 7687.975us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.950s 7687.975us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.950s 7687.975us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.950s 7687.975us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.740s 54.156us 200 200 100.00
edn_sec_cm 9.950s 7687.975us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.740s 54.156us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.500s 321.583us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 122.710s 4924.506us 50 50 100.00

Error Messages

   Test seed line log context