Simulation Results: hmac

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.97 %
  • code
  • 99.30 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 11.440s 1283.929us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.210s 104.847us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.210s 236.901us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 10.020s 902.486us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.390s 1502.690us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 585.390s 127674.602us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.210s 236.901us 20 20 100.00
hmac_csr_aliasing 6.390s 1502.690us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 86.770s 34168.162us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 87.200s 7680.267us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 239.020s 6632.904us 30 30 100.00
hmac_test_sha384_vectors 535.320s 60003.235us 75 75 100.00
hmac_test_sha512_vectors 543.650s 15965.906us 75 75 100.00
hmac_test_hmac256_vectors 14.670s 344.506us 50 50 100.00
hmac_test_hmac384_vectors 17.110s 535.513us 60 60 100.00
hmac_test_hmac512_vectors 20.810s 908.725us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 37.300s 10746.495us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1018.470s 12417.763us 10 10 100.00
error 10 10 100.00
hmac_error 108.450s 2772.982us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 92.450s 69807.420us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 11.440s 1283.929us 10 10 100.00
hmac_long_msg 86.770s 34168.162us 10 10 100.00
hmac_back_pressure 87.200s 7680.267us 25 25 100.00
hmac_datapath_stress 1018.470s 12417.763us 10 10 100.00
hmac_burst_wr 37.300s 10746.495us 50 50 100.00
hmac_stress_all 2270.810s 29980.137us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 11.440s 1283.929us 10 10 100.00
hmac_long_msg 86.770s 34168.162us 10 10 100.00
hmac_back_pressure 87.200s 7680.267us 25 25 100.00
hmac_datapath_stress 1018.470s 12417.763us 10 10 100.00
hmac_wipe_secret 92.450s 69807.420us 10 10 100.00
hmac_test_sha256_vectors 239.020s 6632.904us 30 30 100.00
hmac_test_sha384_vectors 535.320s 60003.235us 75 75 100.00
hmac_test_sha512_vectors 543.650s 15965.906us 75 75 100.00
hmac_test_hmac256_vectors 14.670s 344.506us 50 50 100.00
hmac_test_hmac384_vectors 17.110s 535.513us 60 60 100.00
hmac_test_hmac512_vectors 20.810s 908.725us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 11.440s 1283.929us 10 10 100.00
hmac_long_msg 86.770s 34168.162us 10 10 100.00
hmac_back_pressure 87.200s 7680.267us 25 25 100.00
hmac_datapath_stress 1018.470s 12417.763us 10 10 100.00
hmac_burst_wr 37.300s 10746.495us 50 50 100.00
hmac_error 108.450s 2772.982us 10 10 100.00
hmac_wipe_secret 92.450s 69807.420us 10 10 100.00
hmac_test_sha256_vectors 239.020s 6632.904us 30 30 100.00
hmac_test_sha384_vectors 535.320s 60003.235us 75 75 100.00
hmac_test_sha512_vectors 543.650s 15965.906us 75 75 100.00
hmac_test_hmac256_vectors 14.670s 344.506us 50 50 100.00
hmac_test_hmac384_vectors 17.110s 535.513us 60 60 100.00
hmac_test_hmac512_vectors 20.810s 908.725us 75 75 100.00
hmac_stress_all 2270.810s 29980.137us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2270.810s 29980.137us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 95.077us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.940s 61.002us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.800s 470.114us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.800s 470.114us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.210s 104.847us 5 5 100.00
hmac_csr_rw 1.210s 236.901us 20 20 100.00
hmac_csr_aliasing 6.390s 1502.690us 5 5 100.00
hmac_same_csr_outstanding 2.780s 144.077us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.210s 104.847us 5 5 100.00
hmac_csr_rw 1.210s 236.901us 20 20 100.00
hmac_csr_aliasing 6.390s 1502.690us 5 5 100.00
hmac_same_csr_outstanding 2.780s 144.077us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.520s 359.728us 5 5 100.00
hmac_tl_intg_err 4.470s 225.709us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.470s 225.709us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 11.440s 1283.929us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.430s 118.690us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 475.780s 23027.923us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.240s 151.860us 1 1 100.00

Error Messages

   Test seed line log context