Simulation Results: keymgr

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 98.96 %
  • assert
  • 97.72 %
  • func
  • 91.13 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 98.22 %
  • toggle
  • 98.42 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.29%
V2S
99.51%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 34.220s 14197.347us 50 50 100.00
random 50 50 100.00
keymgr_random 49.690s 21594.300us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 2.100s 59.550us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.850s 30.599us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 14.540s 1007.967us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 11.720s 366.817us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.600s 63.589us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.850s 30.599us 20 20 100.00
keymgr_csr_aliasing 11.720s 366.817us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 118.030s 11099.552us 49 50 98.00
sideload 200 200 100.00
keymgr_sideload 29.530s 4793.764us 50 50 100.00
keymgr_sideload_kmac 35.470s 3282.572us 50 50 100.00
keymgr_sideload_aes 27.180s 8203.281us 50 50 100.00
keymgr_sideload_otbn 22.220s 1141.449us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 42.710s 2563.555us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 8.290s 516.415us 49 50 98.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 7.260s 1731.656us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 42.480s 4870.121us 50 50 100.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 26.110s 1109.199us 49 50 98.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 12.050s 1158.349us 49 50 98.00
stress_all 48 50 96.00
keymgr_stress_all 350.440s 69629.191us 48 50 96.00
intr_test 50 50 100.00
keymgr_intr_test 1.200s 27.230us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.360s 19.560us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.460s 584.829us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.460s 584.829us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 2.100s 59.550us 5 5 100.00
keymgr_csr_rw 1.850s 30.599us 20 20 100.00
keymgr_csr_aliasing 11.720s 366.817us 5 5 100.00
keymgr_same_csr_outstanding 4.170s 406.950us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 2.100s 59.550us 5 5 100.00
keymgr_csr_rw 1.850s 30.599us 20 20 100.00
keymgr_csr_aliasing 11.720s 366.817us 5 5 100.00
keymgr_same_csr_outstanding 4.170s 406.950us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
keymgr_tl_intg_err 7.150s 1012.142us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.770s 1165.808us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.770s 1165.808us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.770s 1165.808us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.770s 1165.808us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.090s 1006.371us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.150s 1012.142us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.770s 1165.808us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 118.030s 11099.552us 49 50 98.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 49.690s 21594.300us 50 50 100.00
keymgr_csr_rw 1.850s 30.599us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 49.690s 21594.300us 50 50 100.00
keymgr_csr_rw 1.850s 30.599us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 49.690s 21594.300us 50 50 100.00
keymgr_csr_rw 1.850s 30.599us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 8.290s 516.415us 49 50 98.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 26.110s 1109.199us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 26.110s 1109.199us 49 50 98.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 49.690s 21594.300us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 16.880s 2382.263us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 11.830s 450.893us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 8.290s 516.415us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.830s 450.893us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.830s 450.893us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.830s 450.893us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.980s 1046.015us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 11.830s 450.893us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 50 60.00
keymgr_stress_all_with_rand_reset 24.390s 399.467us 30 50 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 3081960751738923613261694194082855556138569828976163771709524697550091746094 1275
UVM_ERROR @ 651501674 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 651501674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46708141043648105195307864944461335233535665576930152421785906269877365658764 94
UVM_ERROR @ 713383138 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 713383138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 53479643945573558137610058227470297710117526534421364742663533233387496809389 702
UVM_ERROR @ 1233224883 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1233224883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 28868457996343679558307833723391251059631048223474269100866872174227267160400 1149
UVM_ERROR @ 1247603179 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1247603179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43878011482802285051375723106255449979932241247736059675160262519002436446691 212
UVM_ERROR @ 145098528 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 145098528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 80870482557294614909355992449885402673142983303379537852631368604198035540144 340
UVM_ERROR @ 873209010 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 873209010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 14210894458080383182752257442519053361671078579938338644058869765647484866778 103
UVM_ERROR @ 228205904 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 228205904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 37891118693048226545504328981321316260950557563911482407466304777297876927143 283
UVM_ERROR @ 266787815 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 266787815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 107493916745478891144040725546972211233643059140794194119732669607338873030630 140
UVM_ERROR @ 124567439 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 124567439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 50760808808930804184302923102054513611157362626847922875954900376563344796099 136
UVM_ERROR @ 814302046 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 814302046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 105554740545860321036365359478264569198309721349640613190742622795664368339164 432
UVM_ERROR @ 160446878 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 160446878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 73128845653142985790139068011573323464931850841224642939994480964310062453328 985
UVM_ERROR @ 1822078009 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1822078009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 89093088188863793912159840141290332194591458943382376167291023795762228147149 251
UVM_ERROR @ 871438745 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 871438745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 94852464455645955541066112677188731116769535663551433212980845241335285506219 207
UVM_ERROR @ 500745270 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 500745270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 106775502898352226227746384477392368061970924732663747848665325456952187020961 99
UVM_ERROR @ 585455185 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 585455185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 106381223992064982025138646447965874438556106759376865021461141967760950325745 905
UVM_ERROR @ 231908307 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 231908307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 38005579669978721895138018647201983342719632585138050668025151540089761313138 160
UVM_ERROR @ 150339681 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 150339681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17466018505893796600702300611626879830714366048572440797549663876916471590953 395
UVM_ERROR @ 164925971 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 164925971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 72543314393424874417874680404318941433497660081698451551701961184826657524868 114
UVM_ERROR @ 241487883 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 241487883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 90731363005052238380366307441532423111172699567890734511236111935851096929990 881
UVM_ERROR @ 3922126703 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3922126703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_sync_async_fault_cross 111956499032366947179574180605477722659446987608922705955605896458785441146371 91
UVM_ERROR @ 2584832 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 2584832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 32008050019214416474043652072627653043720004689823674003485863913144181471150 3290
UVM_ERROR @ 3881831981 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 3881831981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_hwsw_invalid_input 27784894116081533028427211014300544389494822544839041994385603656922924042513 203
UVM_ERROR @ 8666107 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 8666107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Attestation Kmac
keymgr_lc_disable 54032074063824021447788519220396165466836842090182496149619626709120569081420 304
UVM_ERROR @ 113664074 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (9614516079484926992980261701107456032982190268837477151964309896890451248810792062924672517417577680225310460202734848198446402402369891191679481846100613 [0xb792c691c6c61644af15c54b547bddbb6b0839614a18a6d0f43a0eb087d6842bf7cb52b8be9564e29643e0ab08729512cddf3d1ccb69ffea05b2bd9941d6f285] vs 9614516079484926992980261701107456032982190268837477151964309896890451248810792062924672517417577680225310460202734848198446402402369891191679481846100613 [0xb792c691c6c61644af15c54b547bddbb6b0839614a18a6d0f43a0eb087d6842bf7cb52b8be9564e29643e0ab08729512cddf3d1ccb69ffea05b2bd9941d6f285]) KMAC key at state StOwnerKey for Attestation Kmac
UVM_INFO @ 113664074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_stress_all 107650675107408872532032707480734285272399910776175426827899914068590236110904 2251
UVM_ERROR @ 4888550715 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2019367192 [0x785d1918] vs 2019367192 [0x785d1918]) reg name: keymgr_reg_block.sw_share0_output_7
UVM_INFO @ 4888550715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start
keymgr_cfg_regwen 74114396850451960942745625330093502662547586650252567966572684241499401455671 228
UVM_ERROR @ 9359577 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 9359577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---