Simulation Results: keymgr_dpe

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.42 %
  • code
  • 84.25 %
  • assert
  • 97.64 %
  • func
  • 17.36 %
  • line
  • 97.62 %
  • branch
  • 94.61 %
  • cond
  • 90.31 %
  • toggle
  • 63.04 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
99.17%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_dpe_smoke 189.260s 33335.781us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_dpe_csr_hw_reset 1.540s 24.640us 5 5 100.00
csr_rw 20 20 100.00
keymgr_dpe_csr_rw 1.550s 23.055us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_dpe_csr_bit_bash 10.050s 1692.667us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_dpe_csr_aliasing 8.530s 1059.520us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.150s 45.935us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_dpe_csr_rw 1.550s 23.055us 20 20 100.00
keymgr_dpe_csr_aliasing 8.530s 1059.520us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 50 50 100.00
keymgr_dpe_intr_test 1.320s 15.351us 50 50 100.00
alert_test 50 50 100.00
keymgr_dpe_alert_test 1.400s 40.914us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_dpe_tl_errors 6.170s 165.287us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_dpe_tl_errors 6.170s 165.287us 20 20 100.00
tl_d_outstanding_access 49 50 98.00
keymgr_dpe_csr_hw_reset 1.540s 24.640us 5 5 100.00
keymgr_dpe_csr_rw 1.550s 23.055us 20 20 100.00
keymgr_dpe_csr_aliasing 8.530s 1059.520us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.540s 164.268us 19 20 95.00
tl_d_partial_access 49 50 98.00
keymgr_dpe_csr_hw_reset 1.540s 24.640us 5 5 100.00
keymgr_dpe_csr_rw 1.550s 23.055us 20 20 100.00
keymgr_dpe_csr_aliasing 8.530s 1059.520us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.540s 164.268us 19 20 95.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
keymgr_dpe_tl_intg_err 7.490s 250.721us 20 20 100.00
keymgr_dpe_sec_cm 20.660s 2317.912us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.010s 1854.359us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.010s 1854.359us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.010s 1854.359us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 5.010s 1854.359us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 8.180s 1191.358us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 20.660s 2317.912us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 20.660s 2317.912us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:642) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
keymgr_dpe_same_csr_outstanding 16432913595267294116785753445381812710672035939407170960041614941243010489915 77
UVM_ERROR @ 6373948 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0x9ccd8ed0 read out mismatch
UVM_INFO @ 6373948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---