Simulation Results: kmac

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.54 %
  • code
  • 94.07 %
  • assert
  • 97.83 %
  • func
  • 97.71 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 79.58 %
Validation stages
V1
100.00%
V2
99.88%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 82.720s 10758.224us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.150s 19.325us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.020s 286.601us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 11.410s 1037.584us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.150s 1351.736us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.060s 145.102us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.020s 286.601us 20 20 100.00
kmac_csr_aliasing 6.150s 1351.736us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.780s 15.947us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.170s 70.224us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3412.600s 472939.299us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1514.670s 149561.725us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2361.120s 344448.683us 5 5 100.00
kmac_test_vectors_sha3_256 1956.960s 72789.535us 5 5 100.00
kmac_test_vectors_sha3_384 1622.370s 68473.976us 5 5 100.00
kmac_test_vectors_sha3_512 1164.440s 109268.094us 5 5 100.00
kmac_test_vectors_shake_128 2839.300s 766573.681us 5 5 100.00
kmac_test_vectors_shake_256 2120.780s 352697.742us 5 5 100.00
kmac_test_vectors_kmac 3.830s 477.882us 5 5 100.00
kmac_test_vectors_kmac_xof 3.580s 281.998us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 539.960s 86039.769us 50 50 100.00
app 50 50 100.00
kmac_app 341.110s 77818.528us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 272.910s 65687.573us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 362.450s 88192.954us 50 50 100.00
error 49 50 98.00
kmac_error 456.870s 21201.105us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 15.810s 2091.157us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 10.910s 708.562us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 52.480s 1806.740us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 41.190s 635.012us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 67.200s 7889.859us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 52.670s 2408.430us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2960.840s 429750.442us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.900s 44.092us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.260s 32.077us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.050s 171.091us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.050s 171.091us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.150s 19.325us 5 5 100.00
kmac_csr_rw 1.020s 286.601us 20 20 100.00
kmac_csr_aliasing 6.150s 1351.736us 5 5 100.00
kmac_same_csr_outstanding 2.120s 382.027us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.150s 19.325us 5 5 100.00
kmac_csr_rw 1.020s 286.601us 20 20 100.00
kmac_csr_aliasing 6.150s 1351.736us 5 5 100.00
kmac_same_csr_outstanding 2.120s 382.027us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.810s 157.315us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.810s 157.315us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.810s 157.315us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.810s 157.315us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.010s 728.492us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.230s 1898.378us 20 20 100.00
kmac_sec_cm 56.650s 7390.123us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.230s 1898.378us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 52.670s 2408.430us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 82.720s 10758.224us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 539.960s 86039.769us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.810s 157.315us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 56.650s 7390.123us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 56.650s 7390.123us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 56.650s 7390.123us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 82.720s 10758.224us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 52.670s 2408.430us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 56.650s 7390.123us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 252.570s 97332.204us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 82.720s 10758.224us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 258.540s 4823.557us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 91538421281232379082481334932689177271761856711091617994673003132707290619683 348
UVM_ERROR @ 2395849043 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2395849043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 24212009595679468770184897166767872617485118535255545159618678492970602712381 176
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---