Simulation Results: kmac

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 92.34 %
  • assert
  • 97.74 %
  • func
  • 96.12 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.44 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.45%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 65.610s 14602.333us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.460s 31.533us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.480s 135.027us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.390s 1005.876us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.290s 1410.585us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.030s 86.436us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.480s 135.027us 20 20 100.00
kmac_csr_aliasing 8.290s 1410.585us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.070s 14.135us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.760s 412.674us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2662.330s 108427.637us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 897.650s 250673.202us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2117.490s 374768.213us 5 5 100.00
kmac_test_vectors_sha3_256 1528.100s 79105.626us 5 5 100.00
kmac_test_vectors_sha3_384 1356.530s 137155.219us 5 5 100.00
kmac_test_vectors_sha3_512 1043.200s 390745.684us 5 5 100.00
kmac_test_vectors_shake_128 1684.340s 41712.371us 5 5 100.00
kmac_test_vectors_shake_256 1803.170s 86729.084us 5 5 100.00
kmac_test_vectors_kmac 2.780s 91.298us 5 5 100.00
kmac_test_vectors_kmac_xof 3.120s 214.828us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 431.500s 81093.946us 50 50 100.00
app 50 50 100.00
kmac_app 308.360s 25060.178us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 250.570s 14012.891us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 292.630s 14747.278us 50 50 100.00
error 49 50 98.00
kmac_error 396.940s 16754.988us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 13.060s 6290.416us 50 50 100.00
sideload_invalid 38 50 76.00
kmac_sideload_invalid 143.200s 10052.628us 38 50 76.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 35.810s 3541.729us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 32.310s 504.645us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 36.200s 18296.291us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 58.280s 1639.906us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 1809.830s 99668.230us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.170s 180.414us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.180s 21.734us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.300s 347.626us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.300s 347.626us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.460s 31.533us 5 5 100.00
kmac_csr_rw 1.480s 135.027us 20 20 100.00
kmac_csr_aliasing 8.290s 1410.585us 5 5 100.00
kmac_same_csr_outstanding 2.960s 404.424us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.460s 31.533us 5 5 100.00
kmac_csr_rw 1.480s 135.027us 20 20 100.00
kmac_csr_aliasing 8.290s 1410.585us 5 5 100.00
kmac_same_csr_outstanding 2.960s 404.424us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.480s 235.642us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.480s 235.642us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.480s 235.642us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.480s 235.642us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.190s 289.346us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 63.850s 41007.814us 5 5 100.00
kmac_tl_intg_err 5.650s 335.336us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.650s 335.336us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 58.280s 1639.906us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 65.610s 14602.333us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 431.500s 81093.946us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.480s 235.642us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 63.850s 41007.814us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 63.850s 41007.814us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 63.850s 41007.814us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 65.610s 14602.333us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 58.280s 1639.906us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 63.850s 41007.814us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 307.040s 17626.077us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 65.610s 14602.333us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 208.130s 19943.685us 7 10 70.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 95355267778857412297345135916619505714862189167256680596387450647667084904199 192
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 29940832802727799273448221452154064308624859366000758078079093493821108833495 85
UVM_FATAL @ 10165219892 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x70f28000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10165219892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 91110228824114640104840805143197008410969586309964798522455206663260605670548 143
UVM_ERROR @ 2216826724 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2216826724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 28416468119805642572045269416713366337664011610156834836401441384340976221916 165
UVM_ERROR @ 8440047372 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8440047372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 67330136193362278934487783414275449245441651622426693398739916637839663004871 393
UVM_ERROR @ 13702457214 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13702457214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 110451254873736719492101592017209950269368179977221586471751765003646715764227 77
UVM_FATAL @ 10135160483 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7e054000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10135160483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 59204834679587824660476120856866158423189341738877586723112785196936979211531 77
UVM_FATAL @ 10136830852 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3962d000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10136830852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 51316643522502956033063286550262448268433610112593798862281607034164848507448 80
UVM_FATAL @ 10174390329 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x98ef7000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10174390329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 47618241712561964432973831337329695177146908994049990524091857924626704434358 80
UVM_FATAL @ 10052627547 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa0aa3000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10052627547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 24024951832436925831497309128457462700260292768007734503126547928316818631412 81
UVM_FATAL @ 10255119934 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x271d7000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10255119934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 20917990721107897901412885733614524182330480788668529489277251335443372032758 81
UVM_FATAL @ 10059935534 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x50a11000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10059935534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 62299670058677284963342293749975440972373605104873387240972738898675988172349 82
UVM_FATAL @ 10084919584 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x19d5a000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10084919584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33)
kmac_sideload_invalid 113606975019623016217203730563906944500009213823982355884357104160871760795343 111
UVM_FATAL @ 10171702711 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4afc2000, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
UVM_INFO @ 10171702711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 80091689851421601021754495134750749811554466362058567772156870404657977149428 84
UVM_FATAL @ 10129651557 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4387a000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10129651557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 80690657848946471226333958120257038611967736851295885053444569586810460972469 84
UVM_FATAL @ 10109743030 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9fb8f000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10109743030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 113470583534833325063626163550462167685257239501977303622510689822946373960559 76
UVM_FATAL @ 10023313681 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x75d98000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10023313681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---