Simulation Results: mbx

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.72 %
  • code
  • 91.63 %
  • assert
  • 97.01 %
  • func
  • 86.52 %
  • block
  • 96.75 %
  • line
  • 96.71 %
  • branch
  • 92.07 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
99.60%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 2 2 100.00
mbx_smoke 105.000s 29839.420us 2 2 100.00
csr_hw_reset 5 5 100.00
mbx_csr_hw_reset 2.000s 86.809us 5 5 100.00
csr_rw 20 20 100.00
mbx_csr_rw 2.000s 20.293us 20 20 100.00
csr_bit_bash 5 5 100.00
mbx_csr_bit_bash 6.000s 584.949us 5 5 100.00
csr_aliasing 5 5 100.00
mbx_csr_aliasing 2.000s 15.823us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
mbx_csr_mem_rw_with_rand_reset 3.000s 46.309us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
mbx_csr_rw 2.000s 20.293us 20 20 100.00
mbx_csr_aliasing 2.000s 15.823us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 2 2 100.00
mbx_stress 164.000s 47909.451us 2 2 100.00
mbx_max_activity 1 2 50.00
mbx_stress_zero_delays 48.000s 2544.792us 1 2 50.00
mbx_imbx_oob 2 2 100.00
mbx_imbx_oob 26.000s 10286.341us 2 2 100.00
mbx_doe_intr_msg 5 5 100.00
mbx_doe_intr_msg 21.000s 561.231us 5 5 100.00
alert_test 50 50 100.00
mbx_alert_test 2.000s 17.521us 50 50 100.00
intr_test 50 50 100.00
mbx_intr_test 2.000s 51.422us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
mbx_tl_errors 5.000s 135.474us 20 20 100.00
tl_d_illegal_access 20 20 100.00
mbx_tl_errors 5.000s 135.474us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
mbx_csr_hw_reset 2.000s 86.809us 5 5 100.00
mbx_csr_rw 2.000s 20.293us 20 20 100.00
mbx_csr_aliasing 2.000s 15.823us 5 5 100.00
mbx_same_csr_outstanding 2.000s 25.458us 20 20 100.00
tl_d_partial_access 50 50 100.00
mbx_csr_hw_reset 2.000s 86.809us 5 5 100.00
mbx_csr_rw 2.000s 20.293us 20 20 100.00
mbx_csr_aliasing 2.000s 15.823us 5 5 100.00
mbx_same_csr_outstanding 2.000s 25.458us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
mbx_tl_intg_err 4.000s 2106.785us 20 20 100.00
mbx_sec_cm 2.000s 19.932us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 54642821450185902387781708183064683956530737833138861896744617523448279846215 187
UVM_ERROR @ 428954706 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 428954706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---