Simulation Results: otbn

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.86 %
  • code
  • 96.96 %
  • assert
  • 96.61 %
  • func
  • 100.00 %
  • block
  • 99.57 %
  • line
  • 99.68 %
  • branch
  • 94.93 %
  • toggle
  • 93.24 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.59%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 17.000s 47.463us 1 1 100.00
single_binary 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 4.000s 30.902us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 7.000s 26.788us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 8.000s 530.633us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 4.000s 14.692us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 13.000s 82.390us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 7.000s 26.788us 20 20 100.00
otbn_csr_aliasing 4.000s 14.692us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 28.000s 2432.837us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 18.000s 2513.875us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 55.000s 554.289us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 2697.239us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 70.000s 2440.387us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 91.000s 278.381us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 26.000s 76.739us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 9.000s 25.226us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 191.000s 2928.779us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 8.000s 28.606us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 5.000s 18.884us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 8.000s 128.242us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 8.000s 128.242us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 4.000s 30.902us 5 5 100.00
otbn_csr_rw 7.000s 26.788us 20 20 100.00
otbn_csr_aliasing 4.000s 14.692us 5 5 100.00
otbn_same_csr_outstanding 7.000s 25.504us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 4.000s 30.902us 5 5 100.00
otbn_csr_rw 7.000s 26.788us 20 20 100.00
otbn_csr_aliasing 4.000s 14.692us 5 5 100.00
otbn_same_csr_outstanding 7.000s 25.504us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 24 25 96.00
otbn_imem_err 25.000s 116.623us 10 10 100.00
otbn_dmem_err 15.000s 95.418us 14 15 93.33
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 14.000s 102.277us 5 5 100.00
otbn_controller_ispr_rdata_err 54.000s 502.581us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 63.470us 5 5 100.00
otbn_urnd_err 9.000s 33.565us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 10.000s 18.611us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 9.000s 32.199us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 12.000s 68.376us 10 10 100.00
tl_intg_err 23 25 92.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
otbn_tl_intg_err 43.000s 589.938us 20 20 100.00
passthru_mem_tl_intg_err 15 20 75.00
otbn_passthru_mem_tl_intg_err 35.000s 213.233us 15 20 75.00
prim_fsm_check 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
prim_count_check 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 17.000s 47.463us 1 1 100.00
sec_cm_data_mem_integrity 14 15 93.33
otbn_dmem_err 15.000s 95.418us 14 15 93.33
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 25.000s 116.623us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 43.000s 589.938us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 26.000s 76.739us 60 60 100.00
sec_cm_controller_fsm_local_esc 37 40 92.50
otbn_imem_err 25.000s 116.623us 10 10 100.00
otbn_dmem_err 15.000s 95.418us 14 15 93.33
otbn_zero_state_err_urnd 9.000s 25.226us 5 5 100.00
otbn_illegal_mem_acc 10.000s 18.611us 5 5 100.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_controller_fsm_sparse 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 37 40 92.50
otbn_imem_err 25.000s 116.623us 10 10 100.00
otbn_dmem_err 15.000s 95.418us 14 15 93.33
otbn_zero_state_err_urnd 9.000s 25.226us 5 5 100.00
otbn_illegal_mem_acc 10.000s 18.611us 5 5 100.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_scramble_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 26.000s 76.739us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 37 40 92.50
otbn_imem_err 25.000s 116.623us 10 10 100.00
otbn_dmem_err 15.000s 95.418us 14 15 93.33
otbn_zero_state_err_urnd 9.000s 25.226us 5 5 100.00
otbn_illegal_mem_acc 10.000s 18.611us 5 5 100.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 16.000s 28.301us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 12.629us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 34.000s 89.732us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 34.000s 89.732us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 33.621us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_stack_wr_ptr_ctr_redun 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 15.000s 45.927us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_loop_stack_ctr_redun 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 8.000s 37.648us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 8.000s 37.648us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 3 7 42.86
otbn_sec_wipe_err 13.000s 31.191us 3 7 42.86
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 70.000s 2440.387us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 25.000s 382.169us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 253.000s 956.976us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 3 5 60.00
otbn_sec_cm 241.000s 2132.892us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 561.000s 1357.158us 3 10 30.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_dmem_err 5711883029542800371258658558246165915466706937572045584697726211759309093609 None
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 5711883029542800371258658558246165915466706937572045584697726211759309093609 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3801643753 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_dmem_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_dmem_err.3801643753 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_dmem_err.3801643753 -covoverwrite' seed=5711883029542800371258658558246165915466706937572045584697726211759309093609 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_dmem_err_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 5711883029542800371258658558246165915466706937572045584697726211759309093609 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_dmem_err/latest
2026/01/03 05:25:13 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 28323154913468533444515700490643764898002622738885848752330294080015140134772 109
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13994246 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 13994246 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13994246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 38580081273426673404891166946301380770765674687546786433420542164501636789974 106
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 31191386 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 31191386 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 31191386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 27884495447881398387127645205201965014642922944855878746862079058810130861998 108
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 43849902 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 43849902 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 43849902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 28876250735033788646360419283158048599345984444440507149792659990020362607070 106
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 81554110 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 81554110 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 81554110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 14662260807862596864047439256831565469328783304200483299627014338442721380727 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14884156 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 14884156 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14884156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_ctrl_redun 7107298542577812383500983377542277339451869387008803027696573393389234528098 113
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 69235940 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 69235940 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 69235940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 47872484991298143006200695347504032607206359930290706788829104504702195720445 125
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 93790224 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 93790224 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 93790224 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 93790224 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 93790224 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 64179301007328748300395187015144530631231763229934004193304403889188427078151 98
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 71659127 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 71659127 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 71659127 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 71659127 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 71659127 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 107691439936889688608089011932096635464877664266726407040625164251697079493384 261
UVM_ERROR @ 934093176 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 934093176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 8062862695176018802959769683554086103639771307304718915351890217107783256632 234
UVM_ERROR @ 2802309523 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2802309523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 9371434920631121146033405055226495796253945551844284681357912048494509913980 152
UVM_ERROR @ 132419656 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 132419656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 32338137555577394325755843786807783597424390127265113875347279453101438771502 149
UVM_ERROR @ 241420737 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 241420737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 87741275003325089871875706457739911852137476827791398414811275593890212285073 193
UVM_ERROR @ 1041286755 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1041286755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 112939469364105766975425477482881867990054895906129512203939616216297500476264 213
UVM_ERROR @ 941719412 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 941719412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 34728633006651566999157614070958492903283139358529354069491583724948021776924 156
UVM_FATAL @ 34901717 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 34901717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 91663855232851739299651556901758220355350321569224867603798793728755601246588 83
UVM_FATAL @ 3518587 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 3518587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 80987818720537571540404980248334709846356020345121327828035335751006860800063 93
UVM_FATAL @ 67682798 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 67682798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 97036586338558409988998280507860942849351754086448362833515928420434883879899 83
UVM_FATAL @ 1174867 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1174867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 55958603570886380784359247799177597913769073792656548671257817305272454920655 88
UVM_FATAL @ 13070357 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 13070357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 85514172438684428098343171276529787445385744288773088897748945096026341533675 83
UVM_FATAL @ 10858235 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 10858235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---