rom_ctrl Simulation Results

Simulation Results: rom_ctrl

02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.60 %

code
98.74 %

assert
95.49 %

func
98.57 %

line
99.46 %

branch
99.27 %

cond
95.39 %

toggle
99.59 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.53%
V2S		77.99%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	5.640s	306.292us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	9.580s	184.066us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	7.390s	171.928us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	6.220s	170.260us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	4.570s	298.902us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	7.590s	190.825us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	7.390s	171.928us	20	20	100.00
	rom_ctrl_csr_aliasing	4.570s	298.902us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	6.220s	171.779us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	5.470s	925.947us	5	5	100.00

213/214 passed

99.53 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	6.200s	141.607us	2	2	100.00
stress_all				19	20	95.00
	rom_ctrl_stress_all	28.530s	608.648us	19	20	95.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	8.470s	1085.460us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	6.860s	168.685us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	9.770s	398.535us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	9.770s	398.535us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	9.580s	184.066us	5	5	100.00
	rom_ctrl_csr_rw	7.390s	171.928us	20	20	100.00
	rom_ctrl_csr_aliasing	4.570s	298.902us	5	5	100.00
	rom_ctrl_same_csr_outstanding	8.120s	4531.652us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	9.580s	184.066us	5	5	100.00
	rom_ctrl_csr_rw	7.390s	171.928us	20	20	100.00
	rom_ctrl_csr_aliasing	4.570s	298.902us	5	5	100.00
	rom_ctrl_same_csr_outstanding	8.120s	4531.652us	20	20	100.00

V2S

248/318 passed

77.99 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	27.110s	3303.746us	20	20	100.00
tl_intg_err				20	25	80.00
	rom_ctrl_sec_cm	284.300s	1289.710us	0	5	0.00
	rom_ctrl_tl_intg_err	59.360s	970.207us	20	20	100.00
prim_fsm_check				0	5	0.00
	rom_ctrl_sec_cm	284.300s	1289.710us	0	5	0.00
prim_count_check				0	5	0.00
	rom_ctrl_sec_cm	284.300s	1289.710us	0	5	0.00
sec_cm_checker_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_checker_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_checker_fsm_local_esc				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_compare_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_compare_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_compare_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	284.300s	1289.710us	0	5	0.00
sec_cm_fsm_sparse				0	5	0.00
	rom_ctrl_sec_cm	284.300s	1289.710us	0	5	0.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	5.640s	306.292us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	5.640s	306.292us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	5.640s	306.292us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	59.360s	970.207us	20	20	100.00
sec_cm_bus_local_esc				18	22	81.82
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
	rom_ctrl_kmac_err_chk	8.470s	1085.460us	2	2	100.00
sec_cm_mux_mubi				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_mux_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_ctrl_redun				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	122.330s	34188.647us	16	20	80.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	27.110s	3303.746us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	284.300s	1289.710us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	574.000s	11012.808us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	6149561556510427243399853464139004682037408507243422545536869449434542455653	167	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 41064859ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 41064859ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 41064859ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
	rom_ctrl_sec_cm	83537962436774967447050098457144863791207282981003976027927708625018654069965	109	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 29581074ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 29581074ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 29581074ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	86171334977719408447042675637343272405413289323436077360265079367946081776245	111	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 22607994ps failed at 22607994ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 22649661ps failed at 22649661ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	92397496314494978099243370992054918358464840757844327809725459700684758407043	237	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 38084813ps failed at 38084813ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 38084813ps failed at 38084813ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	14650309844004802531161485666977833327218934596567917291048248691086440490450	178	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 26357954ps failed at 26357954ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26357954ps failed at 26357954ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
	rom_ctrl_corrupt_sig_fatal_chk	15335737460575888566031078107870773489256723392431684608016613311870142788442	84	UVM_ERROR @ 5472471187 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 5472471187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	34881794487715383532701137554889454716303286361183824647887370085794527005819	82	UVM_ERROR @ 3397564399 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 3397564399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	4339049680902951102248158761190293101338900485484267890935652940758749983874	94	UVM_ERROR @ 4127431739 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 4127431739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	78158804152798537251347757840912593094623306343807350855731202523055487306431	103	UVM_ERROR @ 2997248491 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 2997248491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
	rom_ctrl_stress_all	97319763208302781415183372673160409157730555917102341722890480853927204595803	76	UVM_ERROR @ 2385151824 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire UVM_INFO @ 2385151824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---