rom_ctrl Simulation Results

Simulation Results: rom_ctrl

02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.54 %

code
99.55 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.64 %

cond
98.66 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		92.45%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	10.260s	307.543us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	14.750s	649.995us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	12.690s	1222.946us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	11.620s	533.953us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	10.950s	306.939us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	13.780s	4161.526us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	12.690s	1222.946us	20	20	100.00
	rom_ctrl_csr_aliasing	10.950s	306.939us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	10.280s	1028.305us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	11.440s	290.114us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	10.470s	926.470us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	53.830s	4217.970us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	17.620s	1060.230us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	15.280s	1545.052us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	16.450s	4182.677us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	16.450s	4182.677us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	14.750s	649.995us	5	5	100.00
	rom_ctrl_csr_rw	12.690s	1222.946us	20	20	100.00
	rom_ctrl_csr_aliasing	10.950s	306.939us	5	5	100.00
	rom_ctrl_same_csr_outstanding	19.350s	1072.347us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	14.750s	649.995us	5	5	100.00
	rom_ctrl_csr_rw	12.690s	1222.946us	20	20	100.00
	rom_ctrl_csr_aliasing	10.950s	306.939us	5	5	100.00
	rom_ctrl_same_csr_outstanding	19.350s	1072.347us	20	20	100.00

V2S

294/318 passed

92.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	52.730s	6349.405us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_sec_cm	572.200s	2633.438us	1	5	20.00
	rom_ctrl_tl_intg_err	130.690s	1206.169us	20	20	100.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	572.200s	2633.438us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	572.200s	2633.438us	1	5	20.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	572.200s	2633.438us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	572.200s	2633.438us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	10.260s	307.543us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	10.260s	307.543us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	10.260s	307.543us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	130.690s	1206.169us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
	rom_ctrl_kmac_err_chk	17.620s	1060.230us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	195.300s	3698.444us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	52.730s	6349.405us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	572.200s	2633.438us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	341.740s	17846.080us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	100155754047172447232508770053669464536027914372033293722644167226026178709114	230	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 42499277ps failed at 42499277ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 42540944ps failed at 42540944ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	86190480847894183084194731788659841766063833573615975851835423557657049412198	300	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 115845914ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 115845914ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 115845914ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	93721900267209170757818684668670838779341657153599478235470283874891530949623	236	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 59732717ps failed at 59732717ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 59732717ps failed at 59732717ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	90612167672604842812072096930095787275138646862440917451440050377947380022420	238	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 168207233ps failed at 168207233ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 168207233ps failed at 168207233ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'