rstmgr_cnsty_chk Simulation Results

Simulation Results: rstmgr_cnsty_chk

02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.52 %

code
95.05 %

assert
100.00 %

line
98.41 %

branch
98.31 %

cond
86.21 %

toggle
100.00 %

FSM
92.31 %

Validation stages

unmapped

70.00%

unmapped

7/10 passed

70.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	10	70.00
	rstmgr_cnsty_chk_test	2.580s	10114.101us	7	10	70.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == *))
	rstmgr_cnsty_chk_test	32879540941551572476358096944733625304192743147043586221288739874707819197895	172	UVM_ERROR @ 1750617855 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1768217855 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1785817855 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1803417855 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1821017855 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	10841826995581555022853978365624291979913814679826991037818189384915609596697	172	UVM_ERROR @ 1956933440 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1976613440 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1996293440 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 2015973440 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 2035653440 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	11348442022377487284640935745616938204599507430675372838428109264388877784451	172	UVM_ERROR @ 1893450555 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1912490555 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1931530555 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1950570555 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1969610555 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16