| V1 |
|
100.00% |
| V2 |
|
94.69% |
| V2S |
|
100.00% |
| V3 |
|
42.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.560s | 1110.294us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.800s | 17.011us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.800s | 15.779us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.740s | 412.092us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 0.960s | 30.996us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.360s | 429.515us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.800s | 15.779us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.960s | 30.996us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 3 | 20 | 15.00 | |||
| rv_timer_random_reset | 6.760s | 6690.512us | 3 | 20 | 15.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 3.440s | 2824.662us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 597.150s | 1701359.251us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 597.150s | 1701359.251us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 5.780s | 4538.500us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.740s | 12.129us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.770s | 45.190us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.040s | 55.332us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.040s | 55.332us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.800s | 17.011us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.800s | 15.779us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.960s | 30.996us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.980s | 17.417us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.800s | 17.011us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.800s | 15.779us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.960s | 30.996us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.980s | 17.417us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.370s | 108.036us | 20 | 20 | 100.00 | |
| rv_timer_sec_cm | 0.910s | 446.643us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.370s | 108.036us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 1.870s | 114.426us | 2 | 10 | 20.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.240s | 673.589us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 15 | 20 | 75.00 | |||
| rv_timer_stress_all_with_rand_reset | 70.060s | 8614.607us | 15 | 20 | 75.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 114741813254435324124774175591881517347664541355663067479412962567291667140729 | 76 |
UVM_FATAL @ 84034457 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5ec56b04) == 0x1
UVM_INFO @ 84034457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 1503222908476810129968786233617651059110441789620050743621285325009687662552 | 73 |
UVM_FATAL @ 331415932 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xecb77704) == 0x1
UVM_INFO @ 331415932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 95753171034014605358244256268895586464495064271555239535037820514059965397102 | 72 |
UVM_FATAL @ 114426133 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa85cad04) == 0x1
UVM_INFO @ 114426133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 38798010376328944983777005080242325788776710101835397030425646047656940672134 | 72 |
UVM_FATAL @ 75125328 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdbf89304) == 0x1
UVM_INFO @ 75125328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35447187796363150456379626928331237927433904384188152355930962110586270512086 | 73 |
UVM_FATAL @ 455868785 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1a4b0b04) == 0x1
UVM_INFO @ 455868785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 58513494967931729686419483573489592294813984141210189092265951126116886426195 | 74 |
UVM_FATAL @ 64985558 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xbab54704) == 0x1
UVM_INFO @ 64985558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 23878241574662402485642624701471570293624796067397557024144251313302900452064 | 73 |
UVM_FATAL @ 226136256 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd6fa6104) == 0x1
UVM_INFO @ 226136256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 92788901323650545652240995915991500389937848868440781657026878041912038518578 | 72 |
UVM_FATAL @ 74047211 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2da56304) == 0x1
UVM_INFO @ 74047211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 46517860339335093367311790664113928175799718049437287776516499677169749635496 | 72 |
UVM_FATAL @ 6690512353 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2ffb3f04) == 0x1
UVM_INFO @ 6690512353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 62073415051218594828965971574207010419997085519306163297894486999469245050700 | 73 |
UVM_FATAL @ 107581170 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd276c704) == 0x1
UVM_INFO @ 107581170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 79514909011909869000474588227547925464660566966511213105113766087321554159015 | 72 |
UVM_FATAL @ 125111340 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf68fa704) == 0x1
UVM_INFO @ 125111340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 6983570865645526865700555070314457582061356113397170635072511073757520414553 | 72 |
UVM_FATAL @ 74383046 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x41891b04) == 0x1
UVM_INFO @ 74383046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 65971730028721011954801141396993872692923795294455164461044326449232967840479 | 72 |
UVM_FATAL @ 630241190 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb9ae5d04) == 0x1
UVM_INFO @ 630241190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 77592897561310125126946339120743915746334556589381762968547963185271593756648 | 72 |
UVM_FATAL @ 61787814 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc2b53304) == 0x1
UVM_INFO @ 61787814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80129349004971651120106524548839556400549135473969909227076296650972431290604 | 73 |
UVM_FATAL @ 735767039 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa3903904) == 0x1
UVM_INFO @ 735767039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 56040358311390254212100815220785956928192857446618610848005692447827941966705 | 72 |
UVM_FATAL @ 115406258 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfc294104) == 0x1
UVM_INFO @ 115406258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80616132236867214070559329179285598693962431839831443340307148815118703195553 | 74 |
UVM_FATAL @ 1595792495 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe2944d04) == 0x1
UVM_INFO @ 1595792495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 41327804924868901208275961331124191049283768164201910032189437816773049717396 | 73 |
UVM_FATAL @ 1786061584 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x71801b04) == 0x1
UVM_INFO @ 1786061584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 4844053557477641840889467471038836191004433830373694864187596980147375614827 | 72 |
UVM_FATAL @ 119039464 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x42274504) == 0x1
UVM_INFO @ 119039464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 21525947790663607542858516880408851083104176725025453851506909205124120827927 | 72 |
UVM_FATAL @ 88404637 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x49d61504) == 0x1
UVM_INFO @ 88404637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 2643057567065631319774890821872799236061779587493210402193274806442928283367 | 72 |
UVM_FATAL @ 3397155959 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x49054304) == 0x1
UVM_INFO @ 3397155959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80405450847441404584191302106909456998664970304233707147581364994608487565567 | 74 |
UVM_FATAL @ 452005539 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x73b29904) == 0x1
UVM_INFO @ 452005539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 3309586096387324865401010597726146880644194049385451510671413984792861950447 | 72 |
UVM_FATAL @ 110385758 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb6cdc704) == 0x1
UVM_INFO @ 110385758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 54224145520616316103039198367129638790720334427570334318282813188043828594305 | 72 |
UVM_FATAL @ 993655634 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd6750704) == 0x1
UVM_INFO @ 993655634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 103846620459229547727850981008513747215119152240794806613329807962197012776748 | 73 |
UVM_FATAL @ 198120669 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa9274904) == 0x1
UVM_INFO @ 198120669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 7858859899998881752771171268191813464250935900792658745333374925395851333832 | 72 |
UVM_ERROR @ 177846436 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 177846436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 10271043150111030421222817255682092855193174474715733051149983757225826371892 | 72 |
UVM_ERROR @ 307111859 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 307111859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 84523630893997802821011946670854972259462888068965334067550470360668186169013 | 74 |
UVM_ERROR @ 158570684 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 158570684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 94032937505639833373834764813962426196641063610852010345215113942000560995370 | 72 |
UVM_ERROR @ 149249933 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 149249933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 18270709858793644463151984252655493067013216743766067486604492524441914069316 | 72 |
UVM_ERROR @ 44413141 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44413141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 78389771342127588464489991608642462499377970973513840207760505909103247912007 | 72 |
UVM_ERROR @ 164636464 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 164636464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64031008242750922947920723494491292078413170244205851767093387437495019236903 | 72 |
UVM_ERROR @ 86310795 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 86310795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 39846125025109965245911053820969811486001562493510366569667256150842564305250 | 72 |
UVM_ERROR @ 303527800 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 303527800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 44949624817405306888663092452436561879365186179178840254412386503805946184601 | 73 |
UVM_ERROR @ 86586082 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 86586082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 54808336506642936735567142362249095778132042823574381128777683589841001447858 | 72 |
UVM_ERROR @ 673588567 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 673588567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 3380320666818779406866167932483497420872630408082067196700516412394412397718 | 221 |
UVM_FATAL @ 8963485590 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 8963485590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 32258020648230347746017103436499915022384594043472174726337019304810787668988 | 104 |
UVM_FATAL @ 1317777964 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1317777964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 37109100681736946416951013927431184073147483795698352828588358878311656808444 | 301 |
UVM_ERROR @ 16885041438 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 16885041438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 1092758832611462386385284958400240841465541257334705809074999091302340735356 | 262 |
UVM_ERROR @ 7615803537 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 7615803537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| rv_timer_stress_all_with_rand_reset | 40491056507080366937208607257516334086234488285121939360953625070631830293894 | 189 |
UVM_ERROR @ 3536006228 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3536006228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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