Simulation Results: spi_host

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.65%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 73.000s 8266.840us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 50.172us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 7.000s 31.605us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 3.000s 55.923us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 98.959us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 35.078us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 7.000s 31.605us 20 20 100.00
spi_host_csr_aliasing 2.000s 98.959us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 22.667us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 40.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 31.000s 35.214us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 33.000s 603.045us 50 50 100.00
spi_host_error_cmd 31.000s 16.918us 50 50 100.00
spi_host_event 150.000s 16257.902us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 33.000s 145.584us 50 50 100.00
speed 50 50 100.00
spi_host_speed 33.000s 145.584us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 33.000s 145.584us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 107.000s 7164.007us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 31.000s 53.144us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 33.000s 145.584us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 33.000s 145.584us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 73.000s 8266.840us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 73.000s 8266.840us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 90.000s 30517.331us 50 50 100.00
spien 50 50 100.00
spi_host_spien 101.000s 29857.738us 50 50 100.00
stall 46 50 92.00
spi_host_status_stall 1807.000s 1000000.000us 46 50 92.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 34.000s 1827.459us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 33.000s 603.045us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 31.000s 15.141us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 15.310us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 105.152us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 105.152us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 50.172us 5 5 100.00
spi_host_csr_rw 7.000s 31.605us 20 20 100.00
spi_host_csr_aliasing 2.000s 98.959us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 63.883us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 50.172us 5 5 100.00
spi_host_csr_rw 7.000s 31.605us 20 20 100.00
spi_host_csr_aliasing 2.000s 98.959us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 63.883us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 31.000s 61.393us 5 5 100.00
spi_host_tl_intg_err 2.000s 293.038us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 293.038us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 524.000s 45931.181us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_status_stall 23417557050523756213823746473490483219355806801683526423720869978918846757187 879
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 40950186584998668100161959867797664743086135494325893339809004310172222366894 957
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 83179115005019630457831804206880642538735280088889493854581733590254011337875 797
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
spi_host_status_stall 87892047990069787163867853153032796688141722116236567655983014061438405875633 2869
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 96433182707 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 96433182707 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=96433183000 ps
UVM_INFO @ 96433182707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---