Simulation Results: sram_ctrl

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.85%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 102.840s 939.485us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.040s 11.870us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.030s 72.475us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.860s 704.966us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.040s 131.058us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.510s 2679.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.030s 72.475us 20 20 100.00
sram_ctrl_csr_aliasing 1.040s 131.058us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 413.470s 276446.595us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 175.810s 11044.909us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1364.440s 37899.798us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 368.230s 6704.719us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2484.200s 174134.479us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1179.700s 84121.727us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 109.840s 54588.213us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1240.340s 121812.693us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 96.080s 531.621us 50 50 100.00
sram_ctrl_partial_access_b2b 627.640s 23085.551us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 101.020s 3063.279us 50 50 100.00
sram_ctrl_throughput_w_partial_write 114.330s 787.269us 50 50 100.00
sram_ctrl_throughput_w_readback 105.010s 3815.969us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1416.430s 5749.016us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.010s 4769.973us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 5981.010s 835828.055us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.050s 18.744us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.880s 233.686us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.880s 233.686us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.040s 11.870us 5 5 100.00
sram_ctrl_csr_rw 1.030s 72.475us 20 20 100.00
sram_ctrl_csr_aliasing 1.040s 131.058us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.240s 86.060us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.040s 11.870us 5 5 100.00
sram_ctrl_csr_rw 1.030s 72.475us 20 20 100.00
sram_ctrl_csr_aliasing 1.040s 131.058us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.240s 86.060us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 64.830s 7114.469us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.170s 20.847us 0 5 0.00
sram_ctrl_tl_intg_err 3.280s 291.317us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.170s 20.847us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.280s 291.317us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1416.430s 5749.016us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1416.430s 5749.016us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.030s 72.475us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1240.340s 121812.693us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1240.340s 121812.693us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1240.340s 121812.693us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 109.840s 54588.213us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 42 50 84.00
sram_ctrl_mubi_enc_err 12.180s 9392.177us 42 50 84.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 64.830s 7114.469us 20 20 100.00
sec_cm_mem_readback 40 50 80.00
sram_ctrl_readback_err 9.090s 2747.367us 40 50 80.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 102.840s 939.485us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 102.840s 939.485us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1240.340s 121812.693us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.170s 20.847us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 109.840s 54588.213us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.170s 20.847us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.170s 20.847us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 102.840s 939.485us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.170s 20.847us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 148.340s 8273.478us 50 50 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 95755585116475799101079420542190986485754078297092327701243876499655254874378 100
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 17986963ps failed at 17986963ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 20846963 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 20846963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
sram_ctrl_sec_cm 71315722162697198196192499190753918773068837400125691426890544560987593396032 98
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3415887ps failed at 3415887ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 14532443 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 14532443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 22403889211421275819299567313352982647028145893731782596167548978688692014408 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 5067537148 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 5067537148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 60869646758806476250659556408263233930598366865744521429963767735432091197329 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 9392176650 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 9392176650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 63844969406429050725899408218068000197821147536375338005163377638704877009940 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 688323859 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 688323859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 19401388919535168949568628040296170601736605199812840139686588393656525474006 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 666369162 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 666369162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 11910510284492354363957712626221520171120361310960724522432565928452399069695 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 775428330 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 775428330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 55093100346810226799055981339840546885965368285996219447294020376459736896551 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2672560035 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2672560035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 29383681058374496267441762613269271775743745141611184445185738235113522709411 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 693547391 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 693547391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 41600987587564336451744615575763256218808783793521212343505682384332313177712 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1314398091 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1314398091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 1256231414609278713836243405742824317202382524606235080064223613425555802808 96
UVM_ERROR @ 5313502 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5313502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 58413774069595205996827416952739353708879003556991593730297714182895489889525 97
UVM_ERROR @ 3564673 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3564673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 232039720347751826977432820481592340627535970272780695529500131633623843894 97
UVM_ERROR @ 3312582 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3312582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 78091549631278970109457485352133837807456434723349459980107277710044349317660 95
UVM_ERROR @ 657149335 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x2b)
UVM_INFO @ 657149335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 26938700433092002483300237154522096363086694546570063502974526018621917519045 95
UVM_ERROR @ 690033954 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x60)
UVM_INFO @ 690033954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 9846438410080227356247037815435141925633762533589741032710202746159862105650 95
UVM_ERROR @ 2823656435 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x14)
UVM_INFO @ 2823656435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 59704632486703768154487869919849602812915617746129408997113243922019190276235 95
UVM_ERROR @ 661741165 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x75) != exp (0x5c)
UVM_INFO @ 661741165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 35511941602316751964130631341783401550538871152969399315301628588136924114252 95
UVM_ERROR @ 663423786 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x45)
UVM_INFO @ 663423786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 65660981727074687409460472269225088355265693164680235190862732684546087982504 95
UVM_ERROR @ 4109297229 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x8) != exp (0x6b)
UVM_INFO @ 4109297229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 59895805288562504245708149734111005743030646462839602838335834530525278212725 95
UVM_ERROR @ 5500316833 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x18)
UVM_INFO @ 5500316833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 96304427257730276653374384266252207303541889799706641320654354576636222057890 95
UVM_ERROR @ 2059814844 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6) != exp (0x7e)
UVM_INFO @ 2059814844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 40884379533855245482810347428273905255155611511920885836522322918364067616605 95
UVM_ERROR @ 688327179 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4c) != exp (0x7f)
UVM_INFO @ 688327179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 10438707842700839598207471497553588074924176706782327270495820448338932988880 95
UVM_ERROR @ 1314494986 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x40) != exp (0x56)
UVM_INFO @ 1314494986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---