Simulation Results: sram_ctrl

 
02/01/2026 17:02:06 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.14 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
98.70%
V2
100.00%
V2S
93.72%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 105.180s 1268.546us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.050s 72.267us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.070s 14.101us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.400s 725.448us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.050s 15.093us 5 5 100.00
csr_mem_rw_with_rand_reset 17 20 85.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.360s 62.042us 17 20 85.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.070s 14.101us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 15.093us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 13.500s 3877.523us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 7.260s 827.630us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1420.420s 20428.035us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 406.600s 6183.807us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 82.410s 15037.951us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1299.230s 27501.958us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 12.360s 2161.251us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1847.560s 28261.843us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 103.070s 685.635us 50 50 100.00
sram_ctrl_partial_access_b2b 530.340s 89928.951us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 95.610s 530.133us 50 50 100.00
sram_ctrl_throughput_w_partial_write 97.280s 771.340us 50 50 100.00
sram_ctrl_throughput_w_readback 99.620s 284.231us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1042.230s 64059.804us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.220s 44.592us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 5357.910s 337265.082us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.070s 41.735us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.500s 138.095us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.500s 138.095us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 72.267us 5 5 100.00
sram_ctrl_csr_rw 1.070s 14.101us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 15.093us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.230s 40.371us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 72.267us 5 5 100.00
sram_ctrl_csr_rw 1.070s 14.101us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 15.093us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.230s 40.371us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.960s 6282.697us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.000s 10.394us 0 5 0.00
sram_ctrl_tl_intg_err 3.090s 556.540us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.000s 10.394us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.090s 556.540us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1042.230s 64059.804us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1042.230s 64059.804us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.070s 14.101us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1847.560s 28261.843us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1847.560s 28261.843us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1847.560s 28261.843us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 12.360s 2161.251us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 44 50 88.00
sram_ctrl_mubi_enc_err 1.540s 124.440us 44 50 88.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.960s 6282.697us 20 20 100.00
sec_cm_mem_readback 37 50 74.00
sram_ctrl_readback_err 1.630s 156.003us 37 50 74.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 105.180s 1268.546us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 105.180s 1268.546us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1847.560s 28261.843us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.000s 10.394us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 12.360s 2161.251us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.000s 10.394us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.000s 10.394us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 105.180s 1268.546us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.000s 10.394us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 414.070s 6717.714us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 39134638628780182583575100735747015492145170403220511542178839673714772757370 95
UVM_ERROR @ 90520932 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x75) != exp (0x1b)
UVM_INFO @ 90520932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 27239616777908228824568704730071371264336466636617813968045012292149236887355 95
UVM_ERROR @ 59166434 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1e) != exp (0x35)
UVM_INFO @ 59166434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 69746545700704208361935097089841446756712292316181267930819542688220088570462 95
UVM_ERROR @ 157783834 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1d) != exp (0x62)
UVM_INFO @ 157783834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 91417510483804661586567604442961307913449443723526659770489239336167840660174 95
UVM_ERROR @ 101614902 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x7)
UVM_INFO @ 101614902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 71216275470451563444312782120028261572024905616874339837407020701106753347329 95
UVM_ERROR @ 102043442 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xd) != exp (0x67)
UVM_INFO @ 102043442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 46574724368186440864157462745673536780636145222761215989489140985560975144955 95
UVM_ERROR @ 92018274 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5f) != exp (0x4f)
UVM_INFO @ 92018274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 94136068219321646076954329335087288613005782720250050403848808964227397961557 95
UVM_ERROR @ 26772426 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3) != exp (0x45)
UVM_INFO @ 26772426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 13718468191877125661313706812230215513868282604509916961862045407831338319365 95
UVM_ERROR @ 51832110 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4c) != exp (0x18)
UVM_INFO @ 51832110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 76867296635085715559493450557631519933219632663530611747607771421585873017475 95
UVM_ERROR @ 54657884 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4) != exp (0x8)
UVM_INFO @ 54657884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 57188841751762975502410198174641184022050169043529320315502460365212804831244 95
UVM_ERROR @ 26433858 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x23) != exp (0x7)
UVM_INFO @ 26433858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 90242374248729954095548409979728798819928353102064805295783767559550283803451 95
UVM_ERROR @ 27993691 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x10) != exp (0xd)
UVM_INFO @ 27993691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 75906452534226222760556191170197532278552520235735987771177463105189789185133 95
UVM_ERROR @ 115384103 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x63)
UVM_INFO @ 115384103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 35677057779831035163531083472743878715315107658352550951849196259935320561773 95
UVM_ERROR @ 25652892 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6b) != exp (0x0)
UVM_INFO @ 25652892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 113824037680383179942025294348626897757484339606808768429960775749352021313613 98
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 10092856 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 10092856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 23863829085694726710379021103378444546112923949425234684246957539376932616462 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 4199611 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 4199611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 60807039522108580228797065847521207493965352215932899572365506058582318666267 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 2113922 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2113922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 73542857628908387166575534683832726399629532921109980188544696298452682331848 99
UVM_ERROR @ 10393720 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 10393720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 20868638885387786114770331853130612468538262357613600335625939808744287929640 97
UVM_ERROR @ 3632998 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3632998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3076) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
sram_ctrl_mubi_enc_err 90024532060017437958950070326387020074541910477948636232325643373483431953621 100
UVM_ERROR @ 48336565 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3076) { a_addr: 'h7b0a76d0 a_data: 'h13 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7a a_opcode: 'h0 a_user: 'h2447d d_param: 'h0 d_source: 'h7a d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 48336565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 12677083436687760302819859373748218211657278263556402347305203894764043217088 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 59995393 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 59995393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 4615259054095716536558881327189030645110875216829729671706526752274200457990 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 134393945 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 134393945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 54640548636494681165930565134665074693946292790348052838945022200750832294528 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 170922563 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 170922563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 91365795683928427673132780070965257188588889221463299723215161554512830400725 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 296562118 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 296562118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 25545120514335767847177539370693415505681892625878947815068854757790662087984 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 103466629 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 103466629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 96978718179714131468077246829988385971889287533475479076089207323124786343335 101
UVM_ERROR @ 204207030 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 204207030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 92322479384819384721549537815838347805880588341087962997382004980402633858326 95
UVM_ERROR @ 94886996 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
UVM_INFO @ 94886996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 89157421697570497972020097724733215547379599110559141258007202307672272069112 95
UVM_ERROR @ 93089164 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
UVM_INFO @ 93089164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---