Simulation Results: ac_range_check

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.28 %
  • code
  • 93.54 %
  • assert
  • 97.63 %
  • func
  • 58.67 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 82.34 %
Validation stages
V1
96.67%
V2
98.71%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 18 20 90.00
ac_range_check_smoke 64.000s 7547.987us 18 20 90.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 89.000s 22709.642us 18 20 90.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 160.336us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 4.000s 186.107us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 62.000s 2197.146us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 34.000s 6402.891us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 25.425us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 4.000s 186.107us 20 20 100.00
ac_range_check_csr_aliasing 34.000s 6402.891us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 5.000s 118.702us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 33.000s 1526.917us 1 1 100.00
stress_all 46 50 92.00
ac_range_check_stress_all 313.000s 45671.129us 46 50 92.00
alert_test 50 50 100.00
ac_range_check_alert_test 3.000s 14.606us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 28.062us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 6.000s 412.135us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 6.000s 412.135us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 160.336us 5 5 100.00
ac_range_check_csr_rw 4.000s 186.107us 20 20 100.00
ac_range_check_csr_aliasing 34.000s 6402.891us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 292.698us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 160.336us 5 5 100.00
ac_range_check_csr_rw 4.000s 186.107us 20 20 100.00
ac_range_check_csr_aliasing 34.000s 6402.891us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 292.698us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1167.982us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1167.982us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1167.982us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1167.982us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 124.000s 6440.518us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 134.793us 5 5 100.00
ac_range_check_tl_intg_err 15.000s 438.249us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 445.000s 6715.621us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 55.000s 7364.627us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke 43373801418315239718816895092597388947060859385096113060554004830668125260657 4399
UVM_ERROR @ 2951620426 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2951620426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 23840256918356331509760271625076444727884520799131189127397943289060636679966 4679
UVM_ERROR @ 941263455 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 941263455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 47172518495673140661412370194690847490612064763042421196123177092093879099191 4233
UVM_ERROR @ 10867957280 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 10867957280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 12296628483922076963280913568487173541278374978344424714365952539320788627820 4131
UVM_ERROR @ 1569075004 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1569075004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 55935616317158628038332950914488390446879911408092578537770364156839862888927 17313
UVM_ERROR @ 2191444360 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2191444360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 60535675214079558359686591727011280687431247567061062003905269012746280179072 9155
UVM_ERROR @ 3663919632 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 3663919632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 10936824188064277076886448605049892251440702289582594424415227827797593834165 17869
UVM_ERROR @ 2051471471 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2051471471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 50447303660759317617758013026224670341008871016603621591419785157108370261900 4268
UVM_ERROR @ 404687449 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 404687449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---