Simulation Results: dma

 
09/01/2026 17:01:39 sha: a18de42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.18 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 79.38 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 1435.698us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 1366.243us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 11.000s 1588.921us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 19.250us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 35.853us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 20.000s 1531.011us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 1800.059us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 3.000s 43.734us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 35.853us 20 20 100.00
dma_csr_aliasing 7.000s 1800.059us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 210.000s 39841.190us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 842.000s 253268.163us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 388.000s 77956.539us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 388.000s 77956.539us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 842.000s 253268.163us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 727.000s 48352.365us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 388.000s 77956.539us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 18.000s 1088.583us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 362.000s 223902.546us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 35.728us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 15.873us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 132.288us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 132.288us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 19.250us 5 5 100.00
dma_csr_rw 2.000s 35.853us 20 20 100.00
dma_csr_aliasing 7.000s 1800.059us 5 5 100.00
dma_same_csr_outstanding 3.000s 41.509us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 19.250us 5 5 100.00
dma_csr_rw 2.000s 35.853us 20 20 100.00
dma_csr_aliasing 7.000s 1800.059us 5 5 100.00
dma_same_csr_outstanding 3.000s 41.509us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 34.000s 1020.346us 5 5 100.00
dma_generic_stress 727.000s 48352.365us 5 5 100.00
dma_handshake_stress 388.000s 77956.539us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 13.000s 1317.807us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 10.502us 5 5 100.00
dma_tl_intg_err 5.000s 1547.824us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 197.000s 18526.948us 25 25 100.00
dma_longer_transfer 815.000s 216360.627us 5 5 100.00
dma_stress_all_with_rand_reset 5.000s 510.871us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 85753857621165968224887803418824779827444938555006930471673053319849837094775 97
UVM_ERROR @ 510870800ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 510870800ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---